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參數(shù)資料
| 型號： | HPC-DEV-ISE2 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | High-Performance Communications MicroController |
| 中文描述： | 高性能通信微控制器 |
| 文件頁數(shù)： | 17/30頁 |
| 文件大?。?/td> | 362K |
| 代理商： | HPC-DEV-ISE2 |
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UART Attention Mode
The HPC46400E UART features an Attention Mode of oper-
ation. This mode of operation enables the HPC46400E to
be networked with other processors. Typically in such envi-
ronments, the messages consist of addresses and actual
data. Addresses are specified by having the ninth bit in the
data frame set to 1. Data in the message is specified by
having the ninth bit in the data frame reset to 0.
The UART monitors the communication stream looking for
addresses. When the data word with the ninth bit set is
received, the UART signals the HPC46400E with an inter-
rupt. The processor then examines the content of the re-
ceiver buffer to decide whether it has been addressed and
whether to accept subsequent data.
Programmable Serial Decoder
Interface
The programmable serial decoder interface allows the two
HDLC channels to be used with devices employing several
popular Time Division Multiplexing (TDM) serial protocols
for point-to-point and multipoint data exchanges. These pro-
tocols combine the ‘B’ and ‘D’ channels onto common
pinsDreceived data, transmit data, clock and Sync, which
normally occurs at an 8 KHz rate and provides framing for
the particular protocol.
The decoder uses the serial link clock and Sync signals to
generate internal enables for the ‘D’ and ‘B’ channels,
thereby allowing the HDLC channels to access the appropri-
ate channel data from the multiplexed link.
Additionally, 64 kbit/s to 56 kbits/s rate adaptation can be
done using the Serial Decoder generated enable signals B1
or B2. The rate adaption to 56 kbits/s is accomplished by
using only the first 7 bits of each B channel time slot for
each TDM frame. The transmitter will insert a ‘‘1’’ in the
eighth bit of each frame. The receiver will only receive the
first seven data bits and skip the eighth bit. See Figure 17
65 kbit/56 kbit Rate Adaption Timing Diagram.
HDLC Channel Description
HDLC/DMA Structure
HDLC 1
HDLC 2
HDLC1
Receive
HDLC1
Transmit
HDLC2
Receive
HDLC2
Transmit
DMAR1
DMAT1
DMAR2
DMAT2
GENERAL INFORMATION
Both HDLC channels on the HPC46400E are identical and
operate up to 4.65 Mbps. When used in an ISDN Basic Rate
access application, HDLC channel
Y
1 has been designated
for use with the 16 kbps D-channel or either B channel and
HDLC
Y
2 can be used with either of the 64 kbps B-chan-
nels. If the ‘D’ and ‘B’ channels are present on a common
serial link, the programmable serial decoder interface gen-
erates the necessary enable signals needed to access the
D and B channel data.
There are two sources for the receive and transmit channel
enable signals. They can be internally generated from the
serial decoder interface or they can be externally enabled.
LAPD, the Link Access Protocol for the D channel is derived
from the X.25 packet switching LAPB protocol. LAPD speci-
fies the procedure for a terminal to use the D channel for
the transfer of call control or user-data information. The pro-
cedure is used in both point-to-point and point-to-multipoint
configurations. On the HPC46400E, the HDLC controller
contains user programmable features that allow for the effi-
cient processing of LAPD Information.
HDLC Channel Pin Description
Each HDLC channel has the following pins associated with
it.
HCK
D HDLC Channel Clock Input Signal.
RX
D Receive Serial Data Input. Data latched on
the negative HCK edge.
REN/RHCK D HDLC Channel Receiver Enable Input/Re-
ceiver Clock Input.
TEN
D HDLC Channel Transmitter Enable Input.
TX
D Transmit Serial Data Output. Data clocked
out on the positive HCK edge. Data (not in-
cluding CRC) is sent LSB first. TRI-STATE
when transmitter not enabled.
CFLG1
D Closing Flag output for Channel 1.
HDLC Functional Description
TRANSMITTER DESCRIPTION
Data is transferred from external memory through the DMA
controller into the transmit buffer register, from which it is
loaded into a 8-bit serial shift register. The CRC is computed
and appended to the frame prior to the closing flag being
transmitted. Data is output at the TX output pin. If no further
transmit commands are given the transmitter sends out con-
tinous flags, aborts, or the idle pattern as selected by the
control register.
An interrupt is generated when the DMA has transferred the
last byte from RAM to the HDLC channel for a particular
message or on a transmit error condition. An associated
transmit status register will contain the status information
indicating the specific interrupt source.
To support transmitting data packets at an ‘‘R’’ interface for
V.120 in synchronous UI mode, to support the use of the
HPC in test equipment, or to support proprietary CRC algo-
rithms the transmitter has the option of preventing the trans-
mitting of the hardware generated CRC bytes.
TRANSMITTER FEATURES
Interframe fill: the transmitter can send either continuous
‘1’s or repeated flags or aborts between the closing flag of
one packet and the opening flag of the next. When the CPU
commands the transmitter to open a new frame, the inter-
frame fill is terminated immediately.
Abort: the abort sequence, a zero followed by seven ones,
will be immediately sent on command from the CPU or on
an underrun condition in the DMA.
Bit/Byte boundaries: The message length between packet
headers may have any number of bits and is not confined to
an integral number of bytes. Three bits in the control regis-
ter are used to indicate the number of valid bits in the last
byte. These bits are loaded by the users software.
RECEIVER DESCRIPTION
Data is input to the receiver on the RX pin. The receive
clock can be externally input at either the HCK pin or the
REN/RHCK pin.
Incoming data is routed through one of several paths de-
pending on whether it is the flag, data, or CRC.
Once the receiver is enabled it waits for the opening flag of
the incoming frame, then starts the zero bit deletion, ad-
17
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HPC-DEV-ISE2-E | High-Performance Communications MicroController |
| HPC-DEV-SYS2-E | CABLE, COAX, RG179, BROWN, 3MM, 25M; Length, Reel (Imperial):82ft; Attenuation, 400MHz:68.90dB; Capacitance:75pF/m; Conductor make-up:7/0.102 mm; Diameter, External:3.00mm; Impedance:75R; Length, Reel (Metric):25m; Resistance, per RoHS Compliant: Yes |
| HPC-DEV-SYS2 | High-Performance Communications MicroController |
| HPC-DEV-WDBC | High-Performance microController with A/D |
| HPC46004VF20 | High-Performance microController with A/D |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HPC-DEV-ISE2-E | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Performance Communications MicroController |
| HPC-DEV-ISE4 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Performance microController with A/D |
| HPC-DEV-ISE-E | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Performance microController with A/D |
| HPC-DEV-SUNC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HPC-DEV-SUNDB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Performance Communications MicroController |
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