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參數(shù)資料
| 型號： | HPA00021DGGR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 14-BIT REGISTERED BUFFER WITH SSTL 2 INPUTS AND OUTPUTS |
| 中文描述： | 14位注冊緩沖區(qū)薩里衛(wèi)星技術(shù)有限公司2輸入和輸出 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大小： | 156K |
| 代理商： | HPA00021DGGR |
SCES344E
–
DECEMBER 2000
–
REVISED NOVEMBER 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 2.5 V
±
0.2 V
UNIT
MIN
MAX
fclock
tw
tact
tinact
Clock frequency
200
MHz
Pulse duration
CLK, CLK high or low
2.5
ns
Differential inputs active time (see Note 5)
22
ns
Differential inputs inactive time (see Note 6)
22
ns
tsu
Set p time
Setup time
Fast slew rate (see Notes 7 and 9)
D t b f
Data before CLK
, CLK
↑
↓
0.75
ns
Slow slew rate (see Notes 8 and 9)
0.9
th
Hold time
Fast slew rate (see Notes 7 and 9)
D t
Data after CLK
, CLK
↑
↓
0.75
ns
Slow slew rate (see Notes 8 and 9)
0.9
For this test condition, VDDQ always is equal to VCC.
NOTES:
5. Data inputs must be held low for a minimum time of tact min, after RESET is taken high.
6. Data and clock inputs must be held at valid levels (not floating) for a minimum time of tinact min, after RESET is taken low.
7. Data signal input slew rate
≥
1 V/ns
8. Data signal input slew rate
≥
0.5 V/ns and
<
1 V/ns
9. CLK, CLK input slew rates are
≥
1 V/ns.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.5 V
±
0.2 V
UNIT
MIN
MAX
fmax
tpd
tPHL
200
MHz
CLK and CLK
Q
1.1
2.8
ns
RESET
Q
5
ns
For this test condition, VDDQ always is equal to VCC.
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