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參數(shù)資料
| 型號(hào)： | HN29W6484DH08TE |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Controller for AND Flash Memory(AND型閃速存儲(chǔ)器控制器) |
| 中文描述： | 控制器及快閃記憶體（及型閃速存儲(chǔ)器控制器） |
| 文件頁數(shù)： | 11/74頁 |
| 文件大小： | 251K |
| 代理商： | HN29W6484DH08TE |
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HN29W6484DH08TE-1
11
Flash Memory Interface Pin Explanation
Signal name
Direction Pin No.
Description
F_DA7 to F_DA0,
F_DB7 to F_DB0
I/O
73, 74, 75, 77,
78, 79, 80, 82,
29, 30, 31, 32,
33, 35, 36, 37
The Flash bus is F_DA0 to F_DA7 and F_DB0 to
F_DB7. This bus is used as command, address and
data bus for Flash memory.
F_CEA10 to F_CEA1,
F_CEB10 to F_CEB1
O
71, 70, 68, 67,
66, 65, 64, 63,
58, 57, 56, 55,
54, 53, 52, 50,
49, 44, 43, 42
Flash chip enable is used to select the Flash memory.
F_OEA_, F_OEB_
O
83, 38
Flash output enable is used to control read data
output from the Flash memory.
F_RDY_1, F_RDY_2
I
85, 40
Flash ready/busy is driven low by Flash memory
during program or erase operation. Flash ready/busy
becomes high impedance at the completion of the
program or erase operation.
F_WEA_, F_WEB_
O
72, 26
Flash write enable is used to strobe command and
address. The command and address are latched at
the rising edge of the Flash write enable.
F_SC_A1, F_SC_A2,
F_SC_B1, F_SC_B2
O
60, 61, 27, 28
Serial clock is used to read memory data and to
strobe programming data. The programming data is
latched at the rising edge of the Serial clock.
F_CDEA_, F_CDEB_
O
84, 39
Command data enable is used to control the
multiplexed Flash bus when Flash write enable is
asserted. Command and data are latched when
Command data enable is low, and Address is latched
when Command data enable is high.
F_RES_
O
41
Flash reset must be kept at V
(Vss
±
0.2V) while Vcc
is turned on and off to prevent Flash memory from
unintentional erase or programming. Flash reset must
be kept at V
(VCC
±
0.2V) after VCC becomes
stable and while Flash memory is in various
operations such as programming, erase and read.
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相關(guān)代理商/技術(shù)參數(shù) |
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