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參數(shù)資料
| 型號： | HMU17JC-35 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字信號處理外設 |
| 英文描述： | 16 x 16-Bit CMOS Parallel Multipliers |
| 中文描述： | 16-BIT, DSP-MULTIPLIER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 225K |
| 代理商： | HMU17JC-35 |
10
AC Electrical Specifications
V
CC
= 5.0V
±
5%, T
A
= 0
o
C to 70
o
C, Note 6
PARAMETER
SYMBOL
TEST
CONDITIONS
HMU16/HMU17-35
HMU16/HMU17-45
UNITS
MIN
MAX
MIN
MAX
Unclocked Multiply Time
t
MUC
-
55
-
70
ns
Clocked Multiply Time
t
MC
-
35
-
45
ns
X, Y, RND Setup Time
t
S
15
-
18
-
ns
X, Y, RND Hold Time
t
H
2
-
2
-
ns
Clock Pulse Width High
t
PWH
10
-
15
-
ns
Clock Pulse Width Low
t
PWL
10
-
15
-
ns
MSPSEL to Product Out
t
PDSEL
-
22
-
25
ns
Output Clock to P
t
PDP
-
22
-
25
ns
Output Clock to Y
t
PDY
-
22
-
25
ns
Three-State Enable Time
t
ENA
Note 4
-
22
-
25
ns
Three-State Disable Time
t
DIS
-
22
-
25
ns
Clock Enable Setup Time
(HMU17 Only)
t
SE
15
-
15
-
ns
Clock Enable Hold Time
(HMU17 Only)
t
HE
2
-
2
-
ns
Clock Low Hold Time CLKXY
Relative to CLKML
(HMU16 Only)
t
HCL
Note 5
0
-
0
-
ns
Output Rise Time
t
r
From 0.8V to 2.0V
-
8
-
8
ns
Output Fall Time
t
f
From 2.0V to 0.8V
-
8
-
8
ns
NOTES:
4. Transition is measured at
±
200mV from steady state voltage with loading specified in AC Test Circuit, V
1
= 1.5V, R
1
= 500
and C
1
= 40pF.
5. To ensure the correct product is entered in the output registers, new data may not be entered into the input registers before the output registers
have been clocked.
6. Refer to AC Test Circuit, with V
1
= 2.4V, R
1
= 500
and C
1
= 40pF.
AC Test Circuit
NOTE: Includes Stray and Jig Capacitance.
AC Testing Input, Output Waveforms
NOTE: AC Testing: All parameters tested as per test circuit. Input
rise and fall times are driven at 1ns/V.
DUT
C
1
(SEE NOTE)
V
1
R
1
0.3V
0V
V
OH
V
OL
1.5V
1.5V
HMU16, HMU17
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