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參數(shù)資料
| 型號： | HMS87C1304AD |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDSO24 |
| 封裝： | SOP-24 |
| 文件頁數(shù)： | 50/70頁 |
| 文件大?。?/td> | 977K |
| 代理商： | HMS87C1304AD |
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HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
50
Preliminary
Jan. 2001
sponding interrupt source is prohibited. Note that PSW
contains also a master enable bit, I-flag, which disables all
interrupts at once.
Figure 15-2 Interrupt Enable Registers and Interrupt Request Registers
When an interrupt is occurred, the I-flag is cleared and dis-
able any further interrupt, the return address and PSW are
pushed into the stack and the PC is vectored to. Once in the
interrupt service routine the source(s) of the interrupt can
be determined by polling the interrupt request flag bits.
The interrupt request flag bit(s) must be cleared by soft-
ware before re-enabling interrupts to avoid recursive inter-
rupts. The Interrupt Request flags are able to be read and
written.
15.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted
or the interrupt latch is cleared to “0” by a reset or an in-
struction. Interrupt acceptance sequence requires 8 f
OSC
(2
μ
s at f
XIN
=4MHz) after the completion of the current in-
struction execution. The interrupt service task is terminat-
ed upon execution of an interrupt return instruction
Reset/Interrupt
Symbol
Priority
Vector Addr.
Hardware Reset
External Interrupt 0
External Interrupt 1
Timer 0
Timer 1
A/D Converter
Watch Dog Timer
Basic Interval Timer
RESET
INT0
INT1
Timer 0
Timer 1
A/D C
WDT
BIT
-
1
2
3
4
5
6
7
FFFE
H
FFFA
H
FFF8
H
FFF6
H
FFF4
H
FFEA
H
FFE8
H
FFE6
H
Table 15-1 Interrupt Priority
IENH
ADDRESS : E2H
RESET VALUE : 0000----
INT0E
INT1E
T0E
T1E
-
-
-
-
Interrupt Enable Register High
IENL
ADDRESS : E3H
RESET VALUE : 000-----
ADE
WDTE
BITE
-
-
-
-
-
Interrupt Enable Register Low
IRQH
ADDRESS : E4H
RESET VALUE : 0000----
INT0IF
INT1IF
T0IF
T1IF
-
-
-
-
Interrupt Request Register High
IRQL
ADDRESS : E5H
RESET VALUE : 000-----
ADIF
WDTIF
BITIF
-
-
-
-
-
Interrupt Request Register Low
0 : Disable
1 : Enable
Enables or disables the interrupt individually
If flag is cleared, the interrupt is disabled.
0 : Not occurred
1 : Interrupt request is occurred
Shows the interrupt occurrence
Preimnary
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