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| 型號： | HMS77C1000A |
| 廠商： | Hynix Semiconductor Inc. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 38/45頁 |
| 文件大小： | 549K |
| 代理商： | HMS77C1000A |
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HMS77C1000A/HMS77C1001A
Oct. 2001 Ver. 2.0
35
A power-up example where RESET is not tied to VDD is
shown in Figure 14-2. VDD is allowed to rise and stabilize
before bringing RESET high. The chip will actually come
out of reset TIRT after RESET goes high and POR, PFDR
is released.
In Figure 14-3, the on-chip Power-On Reset feature is be-
ing used (RESET and VDD are tied together). The VDD is
stable before the internal reset timer times out and there is
no problem in getting a proper reset. However, Figure 14-
4 depicts a problem situation where VDD rises too slowly.
The time between when the IRT senses a high on the RE-
SET/V
PP
pin, and when the RESET/V
PP
pin (and VDD)
actually reach their full value, is too long. In this situation,
when the internal reset timer times out, VDD has not
reached the VDD (min) value and the chip is, therefore, not
guaranteed to function correctly. For such situations, we
recommend that external R circuits be used to achieve
longer POR delay times (Figure 14-5).
Note:
When the device starts normal operation (exits the
reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be meet to
ensure operation. If these conditions are not met,
the device must be held in reset until the operating
conditions are met.
FIGURE 14-3 TIME-OUT SEQUENCE ON POWER-UP (RESET TIOED TO V
DD
): FAST V
DD
RISE TIME
FIGURE 14-4 TIME-OUT SEQUENCE ON POWER-UP (RESET TIOED TO V
DD
): SLOW V
DD
RISE TIME
V
DD
RESET
INTERNAL POR
IRT TIMER-OUT
INTERNAL RESET
T
IRT
V
DD
RESET
INTERNAL POR
IRT TIMER-OUT
INTERNAL RESET
T
IRT
- When V
DD
rise slowly, the T
IRT
time-out expires long before V
DD
has reached its final value.
In this example, the chip will reset properly if, V1
≥
V
DD
min.
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