參數(shù)資料
型號(hào): HMP8156ACNZ
廠商: INTERSIL CORP
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: NTSC/PAL Encoders
中文描述: COLOR SIGNAL ENCODER, PQFP64
封裝: 14 X 14 MM, ROHS COMPLIANT, PLASTIC, MS-022BE, MQFP-64
文件頁數(shù): 23/34頁
文件大小: 559K
代理商: HMP8156ACNZ
23
4343.4
November 4, 2005
TABLE 29. FIELD CONTROL REGISTER 1
SUB ADDRESS = 26
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Field Detect
Window Size Low
This 8-bit register is cascaded with Field Detect Window Size High to form a 9-bit Field Detect
Window Size value. The value specifies the number of 1X clock cycles in the detection window
before and after the selected edge of VSYNC. It may range from 0 to 511. If the leading edge
of HSYNC occurs within the window, it is the start of an odd or even field, as specified by the
FIELD Detect Select bit. This register is ignored unless HSYNC and VSYNC are configured
as inputs.
80
H
TABLE 30. FIELD CONTROL REGISTER 2
SUB ADDRESS = 27
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-4
Half Line Count
Reset Value
These bits specify the value to load to the vertical half line counter when the selected edge of
VSYNC. The value is ignored when HSYNC and VSYNC are configured as outputs.
00000
B
2
VSYNC Edge
Select
This bit specifies whether the encoder uses the leading or trailing edge of VSYNC to determine
the field and to reset the half line counter. It is ignored unless HSYNC and VSYNC are config-
ured as inputs.
0 = leading edge
1 = trailing edge
0
B
1
FIELD Detect
Select
This bit specifies whether an odd or even field is starting when the leading edge of HSYNC
occurs within the FIELD Detect Window. It is ignored unless HSYNC and VSYNC are config-
ured as inputs.
0 = odd field
1 = even field
0
B
0
Field Detect
Window Size High
This bit is cascaded with Field Detect Window Size Low to form a 9-bit Field Detect Window Size
value. This bit is ignored unless HSYNC and VSYNC are configured as inputs.
0
B
HMP8154, HMP8156A
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