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參數資料
| 型號： | HMP8156ACN |
| 廠商： | INTERSIL CORP |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | NTSC/PAL Encoders |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 封裝： | 14 X 14 MM, PLASTIC, MS-022BE, MQFP-64 |
| 文件頁數： | 22/40頁 |
| 文件大?。?/td> | 563K |
| 代理商： | HMP8156ACN |
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22
Pin Description
NAME
PQFP PIN
NUMBER
INPUT/
OUTPUT
DESCRIPTION
LIN[0:2]
5, 6, 7
Input
Analog Video Inputs. Inputs 0 and 1 are composite inputs. Input 2 can be either a
composite input or the Y component of an S-Video signal.
CIN
19
Input
Analog Chroma input component of an S-Video Input.
WPE
27
Input
White Peak Enable. When enabled (‘1’), the video amplifiers gain is reduced when
the digital output code exceeds 248. When disabled (‘0’) the video amplifier will clip
when the A/D reaches code 255.
GAIN_CTRL
28
Input
Gain Control Input. DC voltage to set the video amplifier’s gain.
DEC_T
78
Input
Decoupling for A/D Converter Reference. Connect a 0.01
μ
F and 0.1
μ
F capacitors to
AGND.
DEC_L
30
Input
Decoupling for A/D Converter Reference. Connect a 0.01
μ
F and 0.1
μ
F capacitors to
AGND.
LAGC_CAP
77
Input
Capacitor Connection for Luminance AGC Circuit. Controls the AGC loop time con-
stant.
LCLAMP_CAP
76
Input
Capacitor Connection for Luminance Clamp Circuit. Controls the clamp loop time
constant.
CCLAMP_CAP
29
Input
Capacitor Connection for Chrominance Clamp Circuit. Controls the clamp loop time
constant.
L_ADIN
8
Input
Luminance A/D Converters input from antialiasing filter.
L_OUT
9
Output
Luminance or Composite Analog Video Amplifier output to antialiasing filter.
SDA
40
Input/
Output
The serial I
2
C serial input/output data line.
SCL
41
Input
The serial I
2
C serial bus clock line.
CLK
13, 38
Input
Master clock for the decoder. This clock is used to run the internal logic, A/D convert-
ers, and Phase Locked Loops. All I/O pins (except the I
2
C) are synchronous to this
master clock. A 50ppmcrystal should be used with a waveform symmetry of 60/40%
or better.
RESET
34
Input
Asynchronous Reset pin. Master Chip reset to initialize the internal states and set
the internal registers to a known state.
CbCr[0:7]
42, 43, 45,
47-51
Output
CbCr Data Output Port. The chrominance data output port of the decoder. Data is in
unsigned format and can range from 0 to 255. The CbCr data is subsampled to 4:2:2
format. In 4:2:2 format the CbCr bus toggles between Cb and Cr samples with the
first sample of a line always being Cb. The port is designed to minimize external logic
needed to interface to a VRAM Serial Access Port, DRAM or FIFO.
Y[0:7]
54-58, 60, 63,
64
Output
Y Data Output Port. The luminance data output port of the decoder. Data is in un-
signed format and can range from 16 to 255. The port is designed to minimize exter-
nal logic needed to interface to a VRAM Serial Access Port, DRAM or FIFO.
DVLD
66
Output
DataValid. This pin signalswhen validdata isavailableon thedata output ports.This
pin is three-stated after a RESET or software reset and should be pulled high
through a 10K resistor.
HSYNC
71
Output
Horizontal Sync. This video synchronous pulse is generated by the detection of hor-
izontal sync on the video input. In the absence of video, the HSYNC rate is set when
the internal PLL counters overflow. The HSYNC begin and end time can be pro-
grammed and is synchronous to CLK. This pin is three-stated after a RESET or soft-
ware reset and should be pulled high through a 10K resistor.
HMP8112
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HMP8156ACNZ | 功能描述:編碼器、解碼器、復用器和解復用器 W/ANNEAL 64MQFP 0+70 ENCODER RoHS:否 制造商:Micrel 產品:Multiplexers 邏輯系列:CMOS 位數: 線路數量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| HMP8156CN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8156EVAL1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Encoders |
| HMP8156EVAL2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8170 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Encoder |
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