參數(shù)資料
型號(hào)： HMP8115CN
廠(chǎng)商： INTERSIL CORP
元件分類(lèi)： 顏色信號(hào)轉(zhuǎn)換
英文描述： NTSC/PAL Video Decoder
中文描述： COLOR SIGNAL DECODER, PQFP80
封裝： 20 X 14 MM, PLASTIC, QFP-80
文件頁(yè)數(shù)： 33/43頁(yè)
文件大?。?/td> 183K
代理商： HMP8115CN
33
TABLE 40. WSS_CRC_EVEN DATA REGISTER
SUB ADDRESS = 29
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-6
Reserved
00
B
5-0
Even Field
WSS CRC Data
If even field WSS is enabled and present during NTSC operation, this register is loaded
with the six bits of CRC information on line 283. It is always a “000000” during PAL oper-
ation. Data written to this register is ignored.
000000
B
TABLE 41. START H_BLANK LOW REGISTER
SUB ADDRESS = 30
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Assert BLANK
Output Signal
This 8-bit register is cascaded with Start H_Blank High Register to form a 10-bit
start_horizontal_blank REGISTER. It specifies the horizontal count (in 1x clock cycles) at
which to assert BLANK each scan line. Bit 0 is always a “0”, so the start of horizontal
blanking may only be done with two pixel resolution. The leading edge of HSYNC is count
000
H
.
4A
H
TABLE 42. START H_BLANK HIGH REGISTER
SUB ADDRESS = 31
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
15-10
Reserved
000000
B
9-8
Assert BLANK
Output Signal
This 2-bit register is cascaded with Start H_Blank Low Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at
which to assert BLANK each scan line. The leading edge of HSYNC is count 000
H
.
11
B
TABLE 43. END H_BLANK REGISTER
SUB ADDRESS = 32
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Negate BLANK
Output Signal
This 8-bit register specifies the horizontal count (in 1x clock cycles) at which to negate
BLANKeach scan line. Bit 0 is always a “0”, so the end of horizontal blanking may only
be done with two pixel resolution. The leading edge of HSYNC is count 000
H
.
7A
H
TABLE 44. START V_BLANK LOW REGISTER
SUB ADDRESS = 33
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Assert BLANK
Output Signal
This 8-bit register is cascaded with Start V_Blank High Register to form a 9-bit
start_vertical_blank register. It specifies the line number to assert BLANK each field.
For NTSC operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even
fields. For PAL operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even
fields.
02
H
HMP8115
相關(guān)PDF資料
PDF描述
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HMS188CS-20 x8 SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HMP8116 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:NTSC/PAL Video Decoder
HMP8116CN 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:NTSC/PAL Video Decoder
HMP8117 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:NTSC/PAL Video Decoder
HMP8117_07 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:NTSC/PAL Video Decoder
HMP8117CN 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 80PQFP,0+70C NTSC/PAL VIDEO DECODER W/MA RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線(xiàn)路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
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