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參數(shù)資料
| 型號(hào)： | HMD32M32M16G |
| 廠商： | Hanbit Electronics Co.,Ltd. |
| 英文描述： | 128Mbyte (32Mx32) 72-pin Fast Page Mode 4K Ref. SIMM Design 5V |
| 中文描述： | 128Mbyte（32Mx32）72針快速頁(yè)面模式4K的參考。上海藥物研究所設(shè)計(jì)5V的 |
| 文件頁(yè)數(shù)： | 6/7頁(yè) |
| 文件大?。?/td> | 103K |
| 代理商： | HMD32M32M16G |
HANBit HMD32M32M16G
URL:www.hbe.co.kr
-
6
- HANBit Electronics Co.,Ltd.
REV.1.0 (August.2002)
-5
-6
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNIT
NOTE
Hyper page mode cycle time
t
HPC
20
25
ns
11
/CAS precharge time (Hyper page cycle)
t
CP
8
10
ns
/RAS pulse width (Hyper page cycle)
t
RASP
50
200K
60
200K
ns
/RAS hold time from /CAS precharge
t
RHCP
30
35
ns
/W to RAS precharge time (C-B-R refresh)
t
WRP
10
10
ns
/W to RAS hold time (C-B-R refresh)
t
WRH
10
10
ns
Output data hold time
t
DOH
5
5
ns
Output buffer turn off delay from /RAS
t
REZ
3
13
3
15
ns
6,12
Output buffer turn off delay from W
t
WEZ
3
13
3
15
ns
6
/W to data delay
t
WED
15
15
ns
/W puls width
t
WPE
5
5
ns
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh
cycles before proper device operation is achieved.
2. Input voltage levels are Vih/Vil. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals.
Transition times are measured between V
IH
(min) and V
IL
(max) and are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 1 TTL loads and 100pF.
4. Operation within the t
RCD
(max) limit insures that t
RAC
(max) can be met. t
RCD
(max) is specified as a reference
point only. If t
RCD
is greater than the specified t
RCD
(max) limit, then access time is controlled exclusively by t
CAC
.
5. Assumes that t
RCD
≥
t
RCD
(max).
6. This parameter defines the time at which the output achieves the open circuit and is not referenced for V
OH
or V
OL
.
7. t
WCS
is non-restrictive operating parameter. It is included in the data sheet as electrical characteristics only. If
t
WCS
≥
t
WCS
(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration
of the cycle.
8. Either t
RCH
or t
RRH
must be satisfied for a read cycle.
9. These parameters are referenced to the /CAS leading edge in early write cycles.
10. Operation within the t
RAD
(max) limit insures that t
RAC
(max) can be met. t
RAD
(max) is specified as reference point
only. If t
RAD
is greater than the specified t
RAD
(max) limit access time is controlled by t
AA
.
11. tASC
≥
6ns, Assume t T=2.0ns.
12. If /RAS goes high before /CAS high going, the open circuit condition of the output is achieved by /CAS high going.
If /CAS goes high before /RAS high going , the open circuit condition of the output is achieved by /RAS going.
.
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