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參數(shù)資料
| 型號： | HMA510 |
| 廠商： | Intersil Corporation |
| 英文描述： | 16 x 16-Bit CMOS Parallel Multiplier Accumulator(16 x 16位 CMOS并行乘法器) |
| 中文描述： | 16 × 16位CMOS并行乘加器（16 × 16位的CMOS并行乘法器） |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 36K |
| 代理商： | HMA510 |
3-7
AC Test Circuit
NOTE: Includes Stray and Jig Capacitance
AC Testing Input, Output Waveforms
NOTE: AC Testing: All Parameters tested as per test circuit. Input
rise and fall times are driven at 1ns/V.
Output Delay
T
D
-
25
-
30
ns
Three-State Enable Time
T
ENA
Note 4
-
25
-
30
ns
Three-State Disable Time
T
DIS
Note 4
-
25
-
30
ns
Input Setup Time
T
S
18
-
20
-
ns
Input Hold Time
T
H
2
-
2
-
ns
Clock High Pulse Width
T
PWH
15
-
20
-
ns
Clock Low Pulse Width
T
PWL
15
-
20
-
ns
Output Rise Time
t
R
From 0.8V to 2.0V
-
8
-
8
ns
Output Fall Time
t
F
From 2.0V to 0.8V
-
8
-
8
ns
NOTES:
4. Transition is measured at
±
200mV from steady state voltage with loading specified in AC Test Circuit; V
1
= 1.5V, R
1
= 500
and C
L
= 40pF.
5. For AC Test load, refer to AC Test Circuit with V
1
= 2.4V, R
1
= 500
and C
L
= 40pF.
AC Electrical Specifications
V
CC
= 5.0V
±
5%, T
A
= 0
o
C to 70
o
C
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
HMA510-45
HMA510-55
UNITS
MIN
MAX
MIN
MAX
DUT
C
1
(SEE NOTE)
V
1
R
1
0.3V
0V
V
OH
V
OL
1.5V
1.5V
Timing Diagram
FIGURE 9. SETUP AND HOLD TIME
FIGURE 10. THREE-STATE CONTROL
FIGURE 11. HMA510 TIMING DIAGRAM
FIGURE 12. PRELOAD TIMING DIAGRAM
DATA
INPUT
CLOCK
INPUT
3.0V
1.5V
0V
3.0V
1.5V
0V
t
S
t
H
THREE
STATE
CONTROL
t
DIS
t
ENA
1.5V
OUTPUT
THREE
STATE
HIGH IMPEDANCE
CLKX
CLKY
XIN, YIN
RND, TC
ACC, SUB
t
PWL
t
PWH
t
HCL
t
H
t
S
t
MA
t
D
CLKP
OUTPUT P, Y
t
PWH
t
PWL
CLKP
PREL
OEX
OEM
OEL
OUTPUT
PINS
t
S
t
H
HMA510
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