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參數(shù)資料
| 型號： | HM9264BLP-8L |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 64 k SRAM (8-kword x 8-bit) |
| 中文描述： | 64畝的SRAM（8 - KWord的× 8位） |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 73K |
| 代理商： | HM9264BLP-8L |
HM9264B Series
Write Cycle
HM9264B-8L
HM9264B-10L
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write cycle time
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
t
OHZ
85
—
100
—
ns
Chip selection to end of write
75
—
80
—
ns
2
Address setup time
0
—
0
—
ns
3
Address valid to end of write
75
—
80
—
ns
Write pulse width
55
—
60
—
ns
1, 9
Write recovery time
WE
to output in high-Z
0
—
0
—
ns
4
0
30
0
35
ns
5
Data to write time overlap
40
—
40
—
ns
Data hold from write time
0
—
0
—
ns
Output active from end of write
5
—
5
—
ns
Output disable to output in high-Z
Notes: 1. A write occurs during the overlap of a low
CS1
, and high CS2, and a high
WE
. A write begins
at the latest transition among
CS1
going low,CS2 going high and
WE
going low. A write ends
at the earliest transition among
CS1
going high CS2 going low and
WE
going high. Time t
WP
is
measured from the beginning of write to the end of write.
2. t
CW
is measured from the later of
CS1
going low or CS2 going high to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
is measured from the earliest of
CS1
or
WE
going high or CS2 going low to the end of write
cycle.
5. During this period, I/O pins are in the output state, therefore the input signals of the opposite
phase to the outputs must not be applied.
6. If
CS1
goes low simultaneously with
WE
going low after
WE
goes low, the outputs remain in
high impedance state.
7. Dout is the same phase of the written data in this write cycle.
8. Dout is the read data of the next address
9. In the write cycle with
OE
low fixed, t
WP
must satisfy the following equation to avoid a problem
of data bus contention
t
WP
≥
t
WHZ
max + t
DW
min.
0
30
0
35
ns
5
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