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參數(shù)資料
| 型號： | HM65W8512 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4 M PSRAM (512-kword ×8-bit)(4 M PSRAM (512k字 ×8位)) |
| 中文描述： | 4個M移動存儲芯片（512 KWord的× 8位）（4個M移動存儲芯片（為512k字× 8位）） |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 160K |
| 代理商： | HM65W8512 |
HM65W8512 Series
5
Block Diagram
Refresh
Control
Timing Pulse Gen.
Read Write Control
Address Latch Control
Column Decoder
Column I/O
Memory Matrix
(2048
×
256)
×
8
Row
Decoder
Address
Latch
Control
Input
Data
Control
CE
WE
I/O 7
I/O 0
A0
A10
A11
A18
OE/RFSH
Pin Functions
CE
: Chip Enable (Input)
CE
is a basic clock. RAM is active when
CE
is low, and is on standby when
CE
is high.
A0 to A18: Address Inputs (Input)
A0 to A10 are row addresses and A11 to A18 are column addresses. The entire addresses A0 to A18
are fetched into RAM by the falling edge of
CE
.
OE
/
RFSH
: Output Enable/Refresh (Input)
This pin has two functions. Basically it works as
OE
when
CE
is low, and as
RFSH
when
CE
is high
(in standby mode). After a read or write cycle finishes, refresh does not start if
CE
goes high while
OE
/
RFSH
is held low. In order to start a refresh in standby mode,
OE
/
RFSH
must go high to reset the
refresh circuits of the RAM. After the refresh circuits are reset, the refresh starts when
OE
/
RFSH
goes
low.
I/O0 to I/O7: Input/Output (Inputs and Outputs) These pins are data I/O pins.
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| HM65W8512DFP-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Pseudo-Static RAM |
| HM65W8512DFP-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Pseudo-Static RAM |
| HM65W8512DRR-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Pseudo-Static RAM |
| HM65W8512DRR-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Pseudo-Static RAM |
| HM65W8512DTT-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Pseudo-Static RAM |
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