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參數(shù)資料
| 型號(hào)： | HM658512ALRR-7 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| 中文描述： | 4個(gè)M移動(dòng)存儲(chǔ)芯片（512 KWord的× 8位）2度刷新 |
| 文件頁(yè)數(shù)： | 1/22頁(yè) |
| 文件大小： | 105K |
| 代理商： | HM658512ALRR-7 |
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HM658512A Series
4 M PSRAM (512-kword
×
8-bit)
2 k Refresh
ADE-203-218C(Z)
Rev. 3.0
Nov. 1997
Description
The Hitachi HM658512A is a CMOS pseudo static RAM organized 512-kword
×
8-bit. It realizes higher
density, higher performance and low power consumption by employing 0.8 μm Hi-CMOS process
technology.
It offers low power data retention by self refresh mode. It also offers easy non multiplexed address
interface and easy refresh functions. HM658512A is suitable for handy systems which work with battery
back-up systems.
The device is packaged in a small 525-mil SOP (460-mil body SOP) or a 8
×
20 mm TSOP with thickness
of 1.2 mm, or a 600-mil plastic DIP. High density custom cards made of Tape Carrier Packages are also
available.
Features
Single 5 V (±10%)
High speed
Access time
CE
access time: 70/80/100 ns (max)
Cycle time
Random read/write cycle time:
115/130/160 ns (min)
Low power
Active: 250 mW (typ)
Standby: 200 μW (typ)
Directly TTL compatible
All inputs and outputs
Simple address configuration
Non multiplexed address
Refresh cycle
2048 refresh cycles: 32 ms
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM658512ALRR-7V | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALRR-8 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALRR-8V | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALTT-10 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALTT-10V | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
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