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參數(shù)資料
| 型號： | HM62W8512BLTTI-7 |
| 廠商： | Hitachi,Ltd. |
| 元件分類： | SRAM |
| 英文描述： | 4 M SRAM (512-kword x 8-bit) |
| 中文描述： | 四米的SRAM（512 - KWord的× 8位） |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 58K |
| 代理商： | HM62W8512BLTTI-7 |
HM62W8512BI Series
11
Low V
CC
Data Retention Characteristics
(Ta = –40 to +85
°
C)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions*
2
CS
≥
V
CC
– 0.2 V, Vin
≥
0 V
V
CC
= 3.0 V, Vin
≥
0 V
CS
≥
V
CC
– 0.2 V
See retention waveform
V
CC
for data retention
Data retention current
V
DR
I
CCDR
2
—
—
V
—
0.8*
3
20*
1
μ
A
Chip deselect to data retention time
t
CDR
t
R
0
—
—
ns
Operation recovery time
Notes: 1. For L-version and 10
μ
A (max.) at Ta = –40 to +40
°
C.
2.
CS
controls address buffer,
WE
buffer,
OE
buffer, and Din buffer. In data retention mode, Vin
levels (address,
WE
,
OE
, I/O) can be in the high impedance state.
3. Typical values are at V
CC
= 3.0 V, Ta = +25
°
C and specified loading, and not guaranteed.
4. t
RC
= read cycle time.
t
RC
*
4
—
—
ns
Low V
CC
Data Retention Timing Waveform
(
CS
Controlled)
V
CC
3.0 V
2.4 V
V
DR
0 V
CS
t
CDR
t
R
CS
≥
V
CC
– 0.2 V
Data retention mode
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