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參數(shù)資料
| 型號： | HM62W8128LFP-10 |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 100 ns, PDSO32 |
| 封裝： | 0.525 INCH, PLASTIC, SOP-32 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 84K |
| 代理商： | HM62W8128LFP-10 |
HM62W8128 Series
8
AC Characteristics (Ta = 0 to +70
°C, V
CC = 3.3 V ± 0.3 V, unless otherwise noted.)
Test Conditions
Input pulse levels: 0.4 V to 2.4 V
Input rise and fall time: 5 ns
Input and output timing reference levels: 1.5 V
Output load: 1 TTL Gate and CL (50 pF) (Including scope & jig)
Read Cycle
HM62W8128-10
HM62W8128-12
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Read cycle time
t
RC
100
—
120
—
ns
Address access time
t
AA
—
100
—
120
ns
Chip selection to output valid
t
CO1
—
100
—
120
ns
t
CO2
—
100
—
120
ns
Output enable to output valid
t
OE
—
80
—
100
ns
Chip selection to output in low-Z
t
LZ1
15
—
15
—
ns
2, 3
t
LZ2
15
—
15
—
ns
2, 3
Output enable to output in low-Z
t
OLZ
10
—
10
—
ns
2, 3
Chip deselection to output in high-Z
t
HZ1
0
40
0
50
ns
1, 2, 3
t
HZ2
0
40
0
50
ns
1, 2, 3
Output disable to output in high-Z
t
OHZ
0
40
0
50
ns
1, 2, 3
Output hold from address change
t
OH
15
—
15
—
ns
Notes: 1. t
HZ and t OHZ are defined as the time at which the outputs achieve the open circuit conditions and are
not referred to output voltage levels.
2. At any given temperature and voltage condition, t
HZ max is less than tLZ min both for a given device
and from device to device.
3. This parameter is sampled and not 100% tested.
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