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參數(shù)資料
| 型號： | HM62G18256 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4M Synchronous Fast Static RAM (256k-words ×18-bits)(4M同步快速靜態(tài)RAM(256k字 ×18位)) |
| 中文描述： | 4分同步快速靜態(tài)存儲器（256k -字× 18位）（4分同步快速靜態(tài)隨機存儲器（256k字× 18位）） |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 194K |
| 代理商： | HM62G18256 |
HM62G18256 Series
4
Pin Descriptions
Name
I/O Type
Descriptions
Note
V
DD
V
SS
V
DDQ
V
REF
K
Supply
Core Power Supply
Supply
Ground
Supply
Output Power Supply
Supply
Input Reference : provides input reference voltage
Input
Clock Input. Active high.
K
Input
Clock Input. Active low.
SS
Input
Synchronous Chip Select
SWE
Input
Synchronous Write Enable
SAn
Input
Synchronous Address Input
n=0,1,2...17
SWEx
Input
Synchronous Byte Write Enables
x = a, b
G
Input
Asynchronous Output Enable
ZZ
Input
Power Down Mode Select
ZQ
Input
Output impedance control
1
DQxn
I/O
Synchronous Data Input / Output
x = a, b n=0,1,2...8
M1, M2
Input
Output Protocol Mode Select
TMS
Input
Boundary Scan Test Mode Select
TCK
Input
Boundary Scan Test Clock
TDI
Input
Boundary Scan Test Data Input
TDO
Output
Boundary Scan Test Data Output
NC
—
No Connection
M1
M2
Protocol
V
SS
Notes: 1. ZQ is to be connected to Vss via a resistance RQ where 150
≤
RQ
≤
350
, if ZQ=V
or
open, output buffer impedance will be maximum. A case of minimum impedance, it needs to
connect over 120
between ZQ and Vss.
2. There is 1 protocol with mode pin. Mode control pins( M1 , M2 ) are to be tied either V
DD
or Vss.
The state of the Mode control inputs must be set before power-up and must not change during
device operation. Mode control inputs are not standard inputs and may not meet VIH or VIL
specification.
V
DD
Synchronous register to register operation 2
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