
HM62864 Series
10
Write Cycle
HM62864-5
HM62864-7
Min
70
HM62864-8
Min
85
Parameter
Write cycle time
Symbol Min
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
t
OHZ
Max
Max
Max
Unit
ns
Notes
55
—
—
—
Chip selection to end of write
50
—
60
—
75
—
ns
4
Address setup time
0
—
0
—
0
—
ns
5
Address valid to end of write
50
—
60
—
75
—
ns
Write pulse width
40
—
50
—
55
—
ns
3, 8
Write recovery time
0
—
0
—
0
—
ns
6
Write to output in high-Z
0
20
0
25
0
30
ns
1, 2, 7
Data to write time overlap
30
—
30
—
35
—
ns
Data hold from write time
0
—
0
—
0
—
ns
Output active from end of write
5
—
5
—
5
—
ns
2
Output disable to output in high-Z
Notes: 1. t
and t
are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap of a low
CS1
, a high CS2 and a low
WE
. A write begins at
the latest transition among
CS1
going low, CS2 going high, and
WE
going low. A write ends at
the earliest transition among
CS1
going high, CS2 going low, and
WE
going high. t
WP
is
measured from the beginning of write to the end of write.
4. t
CW
is measured from the later of
CS1
going low or CS2 going high to the end of write.
5. t
AS
is measured from the address valid to the beginning of write.
6. t
is measured from the earliest of
CS1
or
WE
going high or CS2 going low to the end of write
cycle.
7. During this period, I/O pin are in the output state; therefore, the input signals of the opposite
phase to the outputs must not be applied.
8. In the write cycle with
OE
low fixed, t
must satisfy the following equation to avoid a problem
of data bus contention, t
WP
≥
t
WHZ
max + t
DW
min.
0
20
0
25
0
30
ns
1, 2, 7