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參數(shù)資料
| 型號(hào)： | HM628128DI |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 1 M SRAM (128-kword ×8-bit)(1M靜態(tài)RAM (128k字 ×8位)) |
| 中文描述： | 1個(gè)M的SRAM（128 - KWord的× 8位）（100萬(wàn)靜態(tài)隨機(jī)存儲(chǔ)器（128K的字× 8位）） |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大?。?/td> | 75K |
| 代理商： | HM628128DI |
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HM628128DI Series
12
Low V
CC
Data Retention Characteristics
(Ta = –40 to +85
°
C)
Parameter
Symbol
Min
Typ
*
3
Max
Unit
Test conditions
*
2
V
CC
for data retention
V
DR
2.0
—
—
V
Vin
≥
0V
(1) 0 V
≤
CS2
≤
0.2 V or
(2) CS2
≥
V
CC
– 0.2 V
CS1
≥
V
CC
– 0.2 V
V
= 3.0 V, Vin
≥
0 V
(1) 0 V
≤
CS2
≤
0.2 V or
(2) CS2
≥
V
CC
– 0.2 V,
CS1
≥
V
CC
– 0.2 V
See retention waveform
Data retention current
I
CCDR
*
1
—
1.0
50
μ
A
Chip deselect to data retention time
t
CDR
t
R
0
—
—
ns
Operation recovery time
Notes: 1. This characteristic is guaranteed only for L-version, 30
μ
A max. at Ta = –40 to +40
°
C.
2. CS2 controls address buffer,
WE
buffer,
CS1
buffer,
OE
buffer, and Din buffer. If CS2 controls
data retention mode, Vin levels (address,
WE
,
OE
,
CS1
, I/O) can be in the high impedance state. If
CS1
controls data retention mode, CS2 must be CS2
≥
V
– 0.2 V or 0 V
≤
CS2
≤
0.2 V. The
other input levels (address,
WE
,
OE
, I/O) can be in the high impedance state.
3. Typical values are at V
CC
= 3.0 V, Ta = +25
°
C and specified loading, and not guaranteed.
4. t
RC
= read cycle time.
t
RC
*
4
—
—
ns
Low V
CC
Data Retention Timing Waveform (1)
(
CS1
Controlled)
V
CC
4.5 V
2.4 V
V
DR
0 V
CS1
t
CDR
t
R
CS1
≥
V
CC
– 0.2 V
Data retention mode
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| HM628128DLFP-7 | 1 M SRAM (128-kword x 8-bit) |
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|---|---|
| HM628128DLFI7TR | 制造商:MITSUBISHI 功能描述:NEW |
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