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參數(shù)資料
| 型號： | HM6264BLP-10L |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 64 k SRAM (8-kword x 8-bit) |
| 中文描述： | 64畝的SRAM（8 - KWord的× 8位） |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 82K |
| 代理商： | HM6264BLP-10L |
HM6264B Series
Write Timing Waveform (2)
(
OE
Low Fixed) (
OE
= V
IL
)
t
WC
t
AW
t
CW
t
WP
t
AS
t
WHZ
t
OH
t
OW
*2
*1
*3
t
DH
t
DW
*4
Address
CS1
CS2
Dout
Din
WE
t
WR
Valid data
Valid address
High Impedance
Notes:
1.
If
CS1
goes low simultaneously with
WE
going low or after
WE
goes low, the outputs
remain in high impedance state.
Dout is the same phase of the written data in this write cycle.
Dout is the read data of the next address.
If
CS1
is low and CS2 is high during this period, I/O pins are in the output state. Input
signals of opposite phase to the outputs must not be applied to I/O pins.
2.
3.
4.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM6264B | 64 k SRAM (8-kword x 8-bit) |
| HM6264BI | 64k SRAM (8-kword x 8-bit) Wide Temperature Range version |
| HM6264BLP-8L | 64 k SRAM (8-kword x 8-bit) |
| HM6264BLPI-10 | 64k SRAM (8-kword x 8-bit) Wide Temperature Range version |
| HM6264BLPI-12 | 64k SRAM (8-kword x 8-bit) Wide Temperature Range version |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM6264BLP-8L | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:64 k SRAM (8-kword x 8-bit) |
| HM6264BLPI-10 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:64k SRAM (8-kword x 8-bit) Wide Temperature Range version |
| HM6264BLPI-12 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:64k SRAM (8-kword x 8-bit) Wide Temperature Range version |
| HM6264BLS-10L | 制造商:Hitachi 功能描述: |
| HM6264BLSP-10L | 制造商:Renesas Electronics 功能描述:8k~8 100ns 5V DIP Bulk |
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