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參數(shù)資料
| 型號(hào)： | HM5425801BTT-75A |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank |
| 中文描述： | 32M X 8 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-66 |
| 文件頁數(shù)： | 26/65頁 |
| 文件大小： | 489K |
| 代理商： | HM5425801BTT-75A |
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HM5425161B, HM5425801B, HM5425401B Series
Data Sheet E0086H20
26
Write operation
: The burst length (BL) and the burst type (BT) of the mode register are referred when a
write command is issued. The burst length (BL) determines the length of a sequential data input by the write
command which can be set to 2, 4, or 8. The latency from write command to data input is fixed to 1. The
starting address of the burst read is defined by the column address (AY0 to AY8; the HM5425161B, AY0 to
AY9; the HM5425801B, AY0 to AY9, AY11; the HM5425401B), the bank select address (BA0/BA1) which
are loaded via the A0 to A12, BA0 to BA1 pins in the cycle when the write command is issued. DQS,
DQSU/DQSL should be input as the strobe for the input-data and DM, DMU/DML as well during burst
operation. t
WPREH
prior to the first rising edge of the DQS, the DQSU/DQSL should be set to Low and t
WPST
after the last falling edge of the data strobe can be set to High-Z. The leading low period of DQS is referred
as write preamble. The last low period of DQS is referred as wrtie postamble.
Write Operation
in1
in0
in1
in2
in3
in0
in1
in2
in3
in4
in5
in6
in7
CLK
CLK
Address
DQS*
Din
BL = 2
BL = 4
BL = 8
Command
BL: Burst length
t1
t0
t2
t3
t3.5
t4
t5
t6
t7
t8
t
RCD
t
WPST
DQS*:DQS,DQSU/DQSL
in0
ACTV
NOP
NOP
NOP
WRITE
t
WPREH
t
WPRES
Row
Column
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