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參數(shù)資料
| 型號： | HM5165805FTT |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 64 MEDO DRAM (8-Mword X 8-bit) 8 k Refresh/4 k Refresh |
| 中文描述： | 64目等內(nèi)存（8 Mword × 8位）8畝刷新/ 4畝刷新 |
| 文件頁數(shù)： | 16/35頁 |
| 文件大?。?/td> | 490K |
| 代理商： | HM5165805FTT |
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HM5164805F Series, HM5165805F Series
16
20.t
(min) can be achieved during a series of EDO page mode write cycles or EDO page mode
read cycles. If both write and read operation are mixed in a EDO page mode
RAS
cycle (EDO
page mode mix cycle (1), (2)), minimum value of
CAS
cycle (t
+ t
+ 2 t
) becomes greater
than the specified t
(min) value. The value of
CAS
cycle time of mixed EDO page mode is
shown in EDO page mode mix cycle (1) and (2).
21.Data output turns off and becomes high impedance from later rising edge of
RAS
and
CAS
.
Hold time and turn off time are specified by the timing specifications of later rising edge of
RAS
and
CAS
between t
OHR
and t
OH
and between t
OFR
and t
OFF
.
22.t
defines the time at which the output level go cross. V
OL
= 0.8 V, V
OH
= 2.0 V of output timing
reference level.
23.Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64
ms period on the condition a and b below.
a. Enter self refresh mode within 15.6
μ
s after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within
15.6
μ
s after exiting from self refresh mode.
24.In case of entering from
RAS
-only-refresh, it is necessary to execute CBR refresh before and
after self refresh mode according as note 23.
25 At t
> 100
μ
s, self refresh mode is activated, and not activated at t
< 10
μ
s. It is undefined
within the range of 10
μ
s
≤
t
RASS
≤
100
μ
s. For t
RASS
≥
10
μ
s, it is necessary to satisfy t
RPS
.
26.XXX: H or L (H: V
IH
(min)
≤
V
IN
≤
V
IH
(max), L: V
IL
(min)
≤
V
IN
≤
V
IL
(max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied V
IH
or V
IL
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM5164805F | 64 M EDO（Extended Data Output） DRAM(64M 擴展數(shù)據(jù)輸出模式動態(tài)RAM) |
| HM51W16165LJ-5 | 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh |
| HM51W18165LJ-5 | 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh |
| HM51W16165LJ-6 | 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh |
| HM51W18165LJ-6 | 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM51680J | 制造商:TT Electronics / BI Technologies 功能描述:Ind Power Wirewound 68uH 5% 1KHz 3.3A AXL |
| HM51-680J | 制造商:BI Technologies (TT electronics) 功能描述:Ind Power Wirewound 68uH 5% 1KHz 3.3A AXL |
| HM51-680JLF | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Axially Leaded Miniature Power Inductors |
| HM51680K | 制造商:TT Electronics / BI Technologies 功能描述:Ind Power Wirewound 68uH 10% 1KHz 3.3A AXL |
| HM51-680K | 制造商:BI Technologies (TT electronics) 功能描述:Ind Power Wirewound 68uH 10% 1KHz 3.3A AXL |
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