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參數(shù)資料
| 型號： | HM1-6504B883 |
| 廠商： | Intersil Corporation |
| 英文描述： | 4096 x 1 CMOS RAM |
| 中文描述： | 4096 × 1 CMOS存儲器 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 167K |
| 代理商： | HM1-6504B883 |
6-139
Timing Waveforms
The address information is latched in the on-chip registers
on the falling edge of E (T = 0). Minimum address set up and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1) the output becomes
enabled but the data is not valid until during time (T = 2). W
must remain high for the read cycle. After the output data
has been read, E may return high (T = 3). This will disable
the output buffer and all input, and ready the RAM for the
next memory cycle (T = 4).
TRUTH TABLE
TIME REFERENCE
INPUTS
OUTPUT
FUNCTION
E
W
A
Q
-1
H
X
X
Z
Memory Disabled
0
H
V
Z
Cycle Begins, Addresses are Latched
1
L
H
X
X
Output Enabled
2
L
H
X
V
Output Valid
3
H
X
V
Read Accomplished
4
H
X
X
Z
Prepare for Next Cycle (Same as -1)
5
H
V
Z
Cycle Ends, Next Cycle Begins (Same as 0)
A
(7)
NEXT ADD
TAVEL
(8)
TELAX
(7)
TAVEL
(4) TEHQZ
HIGH Z
VALID DATA OUTPUT
(3)
TELQX
HIGH Z
E
Q
W
HIGH
-1
TIME
0
1
2
3
4
5
REFERENCE
(6)
TEHEL
TELEL (18)
(5)
TELEH
(6)
TEHEL
(1) TELQV
FIGURE 1. READ CYCLE
ADD VALID
HM-6504/883
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PDF描述 |
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| HM1-6508B883 | 1024 x 1 CMOS RAM |
| HM1-6508883 | 1024 x 1 CMOS RAM |
| HM-6508 | 1024 x 1 CMOS RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM1-6504S-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 SRAM |
| HM1-6504S-9 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HM1-6504S-9SR | 制造商:Harris Corporation 功能描述:Static RAM, 4Kx1, 18 Pin, Ceramic, DIP |
| HM-165051-25-8A | 功能描述:電線鑒定 .65/.2IN HM LABEL PRICE PER LABEL RoHS:否 制造商:TE Connectivity / Q-Cees 產(chǎn)品:Labels and Signs 類型: 材料:Vinyl 顏色:Blue 寬度:0.625 in 長度:1 in |
| HM1-6508/883 | 制造商:Harris Corporation 功能描述:Synchronous SRAM, 1K x 1, 16 Pin, Ceramic, DIP |
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