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參數(shù)資料
| 型號： | HIP9021IB |
| 廠商： | INTERSIL CORP |
| 元件分類： | 功率晶體管 |
| 英文描述： | Portable Battery Drive/Torque Controller for N-Channel MOSFETs in Motor Control Systems |
| 中文描述： | 0.018 A BUF OR INV BASED MOSFET DRIVER, PDSO8 |
| 封裝： | PLASTIC, MS-012-AA, SOIC-8 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 59K |
| 代理商： | HIP9021IB |
4
TABLE 1. SWITCH POSITIONS OF FIGURE 1 FOR ELECTRICAL CHARACTERISTIC TESTING
SYMBOL
DRAIN
15K
to 2V
15K
to 2V
15K
to 2V
1V
TRIGGER
OSC
TORQUE
DELAY
GATE
MEASURE
I
DD
+I
OSC
-I
OSC
V
OSC(TH)
V
OSC(TG)
I
TRIGGER
I
TORQUE
I
DELAY1
I
DELAY2
V
DELAY(TH)
GND
3.75V
2V
Open
Open
I
DD
Current Into V
DD
Pin
Source Current From OSC Pin
GND
2.5V
2V
Open
Open
GND
5V
2V
Open
Open
Sink Current Into OSC Pin
Open
1nF
2V
Open
Open
Positive Peak OSC Voltage
1V
Open
1nF
2V
Open
Open
Negative Peak OSC Voltage
15K
to 2V
15K
to 2V
15K
to 2V
15K
to 2V
1V
5V
5V
2V
Open
Open
TRIGGER Leakage Current
Open
5V
5V
Open
Open
TORQUE Leakage Current
7.5V
1nF
Open
1V
Open
Current to DELAY Pin
7.5V
1nF
Open
2V
Open
Current to DELAY Pin
Ramp Up
1nF
2V
GND
Read V
GATE
Measure V
TRIGGER
When
V
GATE
Less Than 0.5V
DRAIN Current; Calculate
R
DRAIN
= 5V/I
DRAIN
DRAIN Current
R
DRAIN
5V
GND
1nF
2V
GND
Open
I
DRAIN
V
GATE
I
GATE
1V
7.5V
5V
2V
Open
Open
5V
GND
1nF
2V
Open
Open
Measure V
GATE
= V
OUT
Measure I
GATE
Source Current
with V
GATE
= V
OUT
-0.5V
GATE Output Slew Rate
2V
GND
1nF
2V
GND
Set to
V
OUT
-0.5V
V
GATE(S/R)
FP/DC
Refer to Figure 2 Application Circuit, 50% GATE Output Duty Cycle
Reference Figure 1 Waveforms
FP/DLY
Reference Figure 1 Waveforms
f
OSC
1V
V
OSC(TH)
-
-1V
1nF
2V
GND
25K
Load
GATE Output Timing
+
-
+
V
GATE
V
DELAY
GND
GND
V
DD
FRAMED PULSE WIDTH
FRAMED PULSE DELAY
GATE PULSE WIDTH
OSC
CONTROL
& LOGIC
DRAIN
TRIGGER
GATE
TORQUE
OSC
DELAY
HIP9021
V
DD
GND
GC
+
3
5
6
8
2
1
4
10nF
15K
10
μ
F
22nF
V
DRAIN
V
TRIGGER
V
DD
V
DELAY
V
OSC
V
TORQUE
V
GATE
1V
2V
10K
R
D
1nF
5V
2V
1V
2V
2V
5V
7.5V
3.75V
2.5V
5V
5V
0.01
μ
F
1nF
1nF
7
NOTE: The timing diagrams relate to the delay output framed pulse and show the time duration of the delay pulse “framed” inside of the gate
pulse. The framed pulse duty cycle and delay, in percent, are measured in reference to the gate pulse which is set at 50% duty cycle. The
Delay output framed pulse delay is one-half of the difference of the gate pulse width minus delay output framed pulse width.
FIGURE 1. ELECTRICAL CHARACTERISTICS TEST CIRCUIT FOR SIGNAL FUNCTIONS OF THE HIP9021
1V
HIP9021
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