FN4367.2 January 6, 2006 INPUT AMPLIFIERS CH0 and CH1 High Output Voltage VOUTHI<" />
參數(shù)資料
型號(hào)： HIP9011ABZ
廠商： Intersil
文件頁(yè)數(shù)： 6/11頁(yè)
文件大小： 0K
描述： IC SENSOR ENGINE KNOCK 20-SOIC
標(biāo)準(zhǔn)包裝： 380
類(lèi)型： 引擎敲擊信號(hào)處理器
輸入類(lèi)型： 邏輯
輸出類(lèi)型： 邏輯
接口： SPI
電流 - 電源： 8mA
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 20-SOIC
包裝： 管件
4
FN4367.2
January 6, 2006
INPUT AMPLIFIERS
CH0 and CH1 High Output Voltage
VOUTHI
ISINK = 100A, VDD = 5.0V
4.7
4.9
-
V
CH0 and CH1 Low Output Voltage
VOUTLO
ISOURCE = 100A; VDD = 5.0V
-
15
200
mV
Voltage Gain
ACL
Input R = 47.5K, Feedback
R = 475k
+18
+20
+21
dB
ANTIALIASING FILTER
Response 1kHz to 20kHz, Referenced to 1kHz
BW
Test Mode
-
-0.5
-
dB
Attenuation at 180kHz, Referenced
to 1kHz
ATTEN
Test Mode
-10
-15
-
dB
PROGRAMMABLE FILTERS
Peak to Peak Voltage Output
VOUT
Run Mode
3.5
4.0
-
VP-P
Filters Q (Note 2)
Q
Run Mode
-
2.5
-
Q
PROGRAMMABLE GAIN AMPLIFIERS
Percent Amplifier Gain Deviation
%G
Run Mode
-
±1-
%
INTEGRATOR
Integrator Reset Voltage
VRESET
Pin 4 Voltage at Start of
Integration
Cycle; VDD = 5.0V
75
125
175
mV
Integrator Droop after 500
sVDROOP
Hold Mode, Pin 7 = 0V,
VDD =5.0V
Pin 4 set to 20% to 80% of VDD
-
±3
±50
mV
DIFFERENTIAL CONVERTER
Differential to Single Ended Converter Offset
Voltage
DIFVIO
By Design
-
0.1
-
mV
Change In Converter Output
DIFOUT
Run Mode, 500
A Sinking Load
to No Load Condition
-
±1
±10
mV
SYSTEM GAIN DEVIATION
Gain Deviation from “Ideal Equation” Correlation
Factor + 5.0% (Note 3)
VOUT -
VRESET
Run Mode, maximum signal
output from Input Amplifier
<2.25VP-P, Equation Output X
0.95 + Device Reset Voltage;
For Total VOUT ≤ 4.7V
-8%,
±100mV
Equatio
n
X 0.95
-
VRESET
8%,
±100mV
V
NOTES:
2. Q = fo/BW, where: fo = Center Frequency, BW = 3dB Bandwidth
3. Ideal Equation: INTOUT (Volts) = [VIN * GIN * GPR * GBPF * 1/π * (N/tC(ms) * fQ(kHz)) * GDSE] + VRESET
Where: VIN = input signal amplitude (VP-P)
GIN = External Input Gain; GIN = RF/RIN
GPR = Programmed Gain
GBPF = Gain of Bandpass Filter (2 for Ideal Case at Center)
tINT = Integration Time; tINT = N/fQ
0.318 = 1/
π
N = Number of Cycles of Input Signal
fQ = Frequency of Input Signal
RF = Feedback Resistor Value
RIN = Signal Input Resistor Value
tC = Programmed Time Constant
GDSE = Gain of DSE Converter (2 for Ideal Case)
VRESET = Integrator Reset Voltage = 0.125V, Typ
Electrical Specifications
VDD = 5V ±5%, GND = 0V, Clock Frequency 4MHz ±0.1%, TA = -40
oC to 125oC,
Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HIP9011
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