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參數(shù)資料
| 型號： | HIP8112A |
| 廠商： | Harris Corporation |
| 英文描述： | NTSC/PAL Video Decoder |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數(shù)： | 8/40頁 |
| 文件大小： | 719K |
| 代理商： | HIP8112A |
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4-8
Internal Phase Locked Loops
The HMP8112A has two independent digital phase locked
loops on chip. A chroma phase-locked loop is implemented
to maintain chroma lock for demodulation of the color chan-
nel, and a line locked phase lock loop is implemented to
maintain vertical spatial alignment. The phase locked loops
are designed to maintain lock even in the event of VCR
headswitches.
The HMP8112A can use a main crystal (CLK) of 20MHz to
30MHz. The crystal is used as a reference frequency for the
internal phase locked loops. The ratio of the crystal fre-
quency to the video standard is programmed into an internal
register for the PLLs to correctly decode video.
The HMP8112A decoder contains 2 sample rate converters
and 2 phase locked loops that lock to the incoming video.
The input sample rate converter synchronizes the digitized
video from the CLK rate to a 4xfSC rate. The chrominance is
separated from the luminance and then demodulated.
The Chroma PLL uses the CLK source as a reference fre-
quency. To initialize the Chroma PLL, the CLK to 4xfSC ratio
value must be loaded into the Chroma PLL Ratio Register
pair. A default 16-Bit Fractional Chroma PLL Ratio Value of
0x87C1 is used after a system RESET is applied. Refer to
Table 1 for example PLL Ratio values to use with the sup-
ported video standards 27MHz or 24.54MHz clocks. Using a
different CLK will require different values to be calculated per
the method shown below. The default assumes a CLK of
27MHz and NTSC as the video standard, and is calculated
as follows:
Ratio =
(4 x fSC) / CLK
(4 x 3.579545MHz) / 27MHz
0.530303
=
=
Register Data: Ratio * 65536
0.530303 * 65536 = 34753.94
0x87C1
Hex Conversion:
The Output Sample Rate converter is locked to the horizon-
tal line frequency and is used to spatially align pixels in a
field. The LOCKED flag signals when the phase locked loop
is within a
±
4 pixel range of the horizontal sync edge. When
line errors exceed that range the LOCKED flag is cleared.
In cases where VCRs are used in Pause, Fast Forward or
Fast Reverse, lines are typically dropped or added by the
VCR. In a worst case scenario a VCR line tolerance will vary
by
±
8%. The standard detect logic checks the line count
against the given standard to determine an error. VCRs in
trick mode cannot cause a standard error. With an NTSC
standard VCR the number of lines in a field should not
O
V
VIDEO
INPUT
LOW TIME
COUNTER
VSYNC
FIELD
VSYNC DETECT THRESHOLD
‘EVEN’ FIELD
APPROX. 5.75 LINES
FIGURE 8. VSYNC TIMING AND THE EVEN TO ODD FIELD TRANSITION
‘ODD’ FIELD
HSYNC
1
LINE #
2
3
4
5
6
7
8
9
10
525
524
1
2
3
4
5
FIGURE 9. VSYNC TIMING AND THE ODD TO EVEN FIELD TRANSITION
O
V
VIDEO
INPUT
LOW TIME
COUNTER
VSYNC
FIELD
VSYNC DETECT THRESHOLD
‘ODD’ FIELD
APPROX. 6.25 LINES
‘EVEN’ FIELD
HSYNC
264
LINE #
265
266
267
268
269
270
271
272
273
263
262
1
2
3
4
5
6
HMP8112A
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