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參數(shù)資料
| 型號： | HIP6602ACR |
| 廠商： | INTERSIL CORP |
| 元件分類： | 功率晶體管 |
| 英文描述： | FPGA 1600000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 0.73 A HALF BRDG BASED MOSFET DRIVER, PQCC16 |
| 封裝： | PLASTIC, MO-220VHHB, MLFP-16 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 250K |
| 代理商： | HIP6602ACR |
7
The power dissipation approximation is a result of power
transferred to and from the upper and lower gates. But, the
internal bootstrap device also dissipates power on-chip
during the refresh cycle. Expressing this power in terms of
the upper MOSFET total gate charge is explained below.
The bootstrap device conducts when the lower MOSFET or
its body diode conducts and pulls the PHASE node toward
GND. While the bootstrap device conducts, a current path is
formed that refreshes the bootstrap capacitor. Since the
upper gate is driving a MOSFET, the charge removed from
the bootstrap capacitor is equivalent to the total gate charge
of the MOSFET. Therefore, the refresh power required by
the bootstrap capacitor is equivalent to the power used to
charge the gate capacitance of the upper MOSFETs.
where Q
LOSS
is the total charge removed from the bootstrap
capacitors and provided to the upper gate loads.
In Figure 1, C
U
and C
L
values are the same and frequency
is varied from 10kHz to 2MHz. PVCC and VCC are tied
together to a +12V supply.
Figure 2 shows the dissipation in the driver with 1nF loading
on both gates and each individually. Figure 3 is the same as
Figure 2 except the capacitance is increased to 3nF.
The impact of loading on power dissipation is shown in
Figure 4. Frequency is held constant while the gate
capacitors are varied from 1nF to 5nF. VCC and PVCC are
tied together and to a +12V supply. Figures 5 through 7
show the same characterization for PVCC tied to +5V
instead of +12V. The gate supply voltage, PVCC, within the
HIP6602A sets both upper and lower gate driver supplies at
the same 5V level for the last three curves.
Test Circuit
P
REFRESH
f
SW
Q
LOSS
V
PVCC
f
SW
Q
U
V
PVCC
=
=
BOOT1
UGATE1
PHASE1
LGATE1
PWM1
PVCC
0.15
μ
F
VCC
0.15
μ
F
100k
2N7002
2N7002
C
L
0.01
μ
F
C
U
+5V OR +12V
+12V
H
UGATE2
PHASE2
LGATE2
100k
2N7002
2N7002
C
L
C
U
0.01
μ
F
PGND
PWM2
GND
BOOT2
+5V OR +12V
Typical Performance Curves
FIGURE 1. POWER DISSIPATION vs FREQUENCY
FIGURE 2. 1nF LOADING PROFILE
1200
1000
800
600
400
200
0
0
500
1000
1500
FREQUENCY (kHz)
P
PVCC = 12V
VCC = 12V
C
U
= C
L
= 2nF
C
U
= C
L
= 1nF
C
U
= C
L
= 3nF
C
U
= C
L
= 4nF
C
U
= C
L
= 5nF
1200
800
600
400
200
0
0
500
1000
2000
FREQUENCY (kHz)
P
1500
PVCC = VCC = 12V
1000
C
U
= C
L
= 1nF
C
L
= 1nF, C
U
= 0nF
C
U
= 1nF, C
L
= 0nF
HIP6602A
相關(guān)PDF資料 |
PDF描述 |
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| HIP6602ACR-T | FPGA 1600000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP6602ACB-T | Dual Channel Synchronous Rectified Buck MOSFET Driver |
| HIRF840 | N-Channel Power MOSFET |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP6602ACR-T | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual Channel Synchronous Rectified Buck MOSFET Driver |
| HIP6602B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual Channel Synchronous Rectified Buck MOSFET Driver |
| HIP6602BCB | 功能描述:IC DRVR MOSF 2CH SYC BUCK 14SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - MOSFET，電橋驅(qū)動器 - 外部開關(guān) 系列:- 標(biāo)準包裝:50 系列:- 配置:低端 輸入類型:非反相 延遲時間:40ns 電流 - 峰:9A 配置數(shù):1 輸出數(shù):1 高端電壓 - 最大（自引導(dǎo)啟動）:- 電源電壓:4.5 V ~ 35 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:TO-263-6，D²Pak（5 引線+接片），TO-263BA 供應(yīng)商設(shè)備封裝:TO-263 包裝:管件 |
| HIP6602BCBT | 制造商:INTERSIL 功能描述:New |
| HIP6602BCB-T | 功能描述:IC DRIVER MOSFET QUAD 14-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - MOSFET，電橋驅(qū)動器 - 外部開關(guān) 系列:- 標(biāo)準包裝:50 系列:- 配置:低端 輸入類型:非反相 延遲時間:40ns 電流 - 峰:9A 配置數(shù):1 輸出數(shù):1 高端電壓 - 最大（自引導(dǎo)啟動）:- 電源電壓:4.5 V ~ 35 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:TO-263-6，D²Pak（5 引線+接片），TO-263BA 供應(yīng)商設(shè)備封裝:TO-263 包裝:管件 |
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