參數(shù)資料
型號(hào)： HIP6521CB-T
廠商： Intersil
文件頁(yè)數(shù)： 8/13頁(yè)
文件大小： 356K
描述： IC REG QD BCK/LINEAR SYNC 16SOIC
標(biāo)準(zhǔn)包裝： 2,500
拓?fù)洌?/td> 降壓（降壓）同步（1），線性（LDO）（3）
功能： 任何功能
輸出數(shù)： 4
頻率 - 開(kāi)關(guān)： 300kHz
電壓/電流 - 輸出 1： 控制器
電壓/電流 - 輸出 2： 控制器
電壓/電流 - 輸出 3： 控制器
帶 LED 驅(qū)動(dòng)器： 無(wú)
帶監(jiān)控器： 無(wú)
帶序列發(fā)生器： 無(wú)
電源電壓： 4.75 V ~ 5.25 V
工作溫度： 0°C ~ 70°C
安裝類型： *
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： *
包裝： 帶卷 (TR)
8
FN4837.5
October 16, 2006
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.
The power components and the controller IC should be
placed first. Locate the input capacitors, especially the
high-frequency ceramic decoupling capacitors, close to the
power switches. Locate the output inductor and output
capacitors between the MOSFETs and the load. Locate the
PWM controller close to the MOSFETs.
The critical small signal components include the bypass
capacitor for VCC and the feedback resistors. Locate these
components close to their connecting pins on the control IC.
A multi-layer printed circuit board is recommended.
Figure 5 shows the connections of the critical components
in the converter. Note that the capacitors C
IN
 and C
OUT
 
each represent numerous physical capacitors. Dedicate
one solid layer for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break
this plane into smaller islands of common voltage levels.
The power plane should support the input power and
output power nodes. Use copper filled polygons on the top
and bottom circuit layers for the PHASE nodes, but do not
unnecessarily oversize these particular islands. Since the
PHASE nodes are subjected to very high dV/dt voltages,
the stray capacitor formed between these islands and the
surrounding circuitry will tend to couple switching noise.
Use the remaining printed circuit layers for small signal
wiring. The wiring traces from the control IC to the
MOSFET gate and source should be sized to carry 2A peak
currents.
PWM Controller Feedback Compensation
The PWM controller uses voltage-mode control for output
regulation. This section highlights the design consideration
for a PWM voltage-mode controller. Apply the methods and
considerations only to the PWM controller.
Figure 6 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the Reference voltage level, 0.8V.
The error amplifier (Error Amp) output (V
E/A
) is compared
with the oscillator (OSC) triangular wave to provide a
pulse-width modulated (PWM) wave with an amplitude of
V
IN
 at the PHASE node. The PWM wave is smoothed by the
output filter (L
O
 and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain, given by V
IN
/V
OSC
, and shaped by the output filter,
with a double pole break frequency at F
LC
 and a zero at
F
ESR
.
FIGURE 5. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
V
OUT1
Q1
Q2
Q3
Q4
+12V
C
VCC
VIA CONNECTION TO GROUND PLANE
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT OR POWER PLANE LAYER
L
OUT
C
OUT1
CR1
HIP6521
C
IN
C
OUT2
V
OUT2
V
OUT3
+5V
IN
PGND
LGATE
UGATE
PHASE
DRIVE3
KEY
GND
VCC
DRIVE2
OCSET
R
OCSET
C
OCSET
V
OUT4
DRIVE4
+3.3V
IN
L
IN
Q5
C
OUT3
C
OUT4
+
+
+
+
+
FIGURE 6. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
OSC
0.8V
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER1
(PARASITIC)
Z
FB
+
-
0.8V
R
S1
R3
R2
C3
C2
C1
COMP
V
OUT
FB
Z
FB
HIP6521
Z
IN
COMP
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
Z
IN
R
P1
SYNC
+
+
HIP6521
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