參數(shù)資料
型號(hào): HIP6503CBZ
廠(chǎng)商: INTERSIL CORP
元件分類(lèi): 電源管理
英文描述: Multiple Linear Power Controller with ACPI Control Interface
中文描述: 9-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO20
封裝: LEAD FREE, PLASTIC, MS-013-AC, SOIC-20
文件頁(yè)數(shù): 5/14頁(yè)
文件大?。?/td> 380K
代理商: HIP6503CBZ
5
FN4882.5
July 21, 2005
DRV2 Output Drive Current
I
DRV2
5VSB = 5V, R
SEL
= 1k
220
-
-
mA
DRV2 Output Impedance
R
SEL
= 10k
-
200
-
3.3V
DUAL
/3.3V
SB
LINEAR REGULATOR (V
OUT3
)
Sleep State Regulation
-
-
2.0
%
3V3DL Nominal Voltage Level
V
3V3DL
-
3.3
-
V
3V3DL Undervoltage Rising Threshold
-
2.739
-
V
3V3DL Undervoltage Hysteresis
-
99
-
mV
3V3DLSB Output Drive Current
I
3V3DLSB
5VSB = 5V
5
10
-
mA
DLA Output Impedance
-
90
-
2.5V
CLK
LINEAR REGULATOR (V
OUT4
)
Regulation
-
-
2.0
%
VCLK Nominal Voltage Level
V
VCLK
-
2.5
-
V
VCLK Undervoltage Rising Threshold
-
2.075
-
V
VCLK Undervoltage Hysteresis
-
75
-
mV
VCLK Output Current (Note 4)
I
VCLK
V
3V3
= 3.3V
500
800
-
mA
5V
DUAL
SWITCH CONTROLLER (V
OUT5
)
5VDL Undervoltage Rising Threshold
-
4.150
-
V
5VDL Undervoltage Hysteresis
-
150
-
mV
5VDLSB Output Drive Current
I
5VDLSB
5VDLSB = 4V, 5VSB = 5V
-20
-
-40
mA
5VDLSB Pull-Up Impedance to 5VSB
-
350
-
TIMING INTERVALS
Active State Assessment Past Input UV
Thresholds (Note 5)
20
25
30
ms
Active-to-Sleep Control Input Delay
-
200
-
μ
s
CONTROL I/O (S3, S5, EN5VDL, FAULT/MSEL)
High Level Input Threshold
-
-
2.2
V
Low Level Input Threshold
0.8
-
-
V
S3, S5 Internal Pull-up Impedance to 5VSB
-
50
-
k
FAULT Output Impedance
FAULT = high
-
100
-
TEMPERATURE MONITOR
Fault-Level Threshold (Note 6)
125
-
-
°C
Shutdown-Level Threshold (Note 6)
-
155
-
°C
NOTES:
2. Sleep-State Only for 3.3V Setting
3. Parameters not guaranteed for 5VSB < 4.0V.
4. At Ambient Temperatures Less Than 50°C.
5. Guaranteed by Correlation.
6. Guaranteed by Design.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HIP6503
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