參數資料
型號: HIP6311ACBZA-T
廠商: INTERSIL CORP
元件分類: 穩(wěn)壓器
英文描述: 150000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
中文描述: SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, PDSO20
封裝: LEAD FREE, PLASTIC, MS-013-AC, SOIC-20
文件頁數: 9/16頁
文件大?。?/td> 449K
代理商: HIP6311ACBZA-T
9
Figure 3 shows the start-up sequence as initiated by a fast
rising 5V supply, V
CC,
applied to the HIP6311A. Note the
short rise to the three state level in PWM 1 output during first
32 PWM cycles.
Figure 4 shows the waveforms when the regulator is
operating at 200kHz. Note that the Soft-Start duration is a
function of the Channel Frequency as explained previously.
Also note the pulses on the COMP terminal. These pulses
are the current correction signal feeding into the comparator
input (see the
Block Diagram
on page 2.)
Figure 5 shows the regulator operating from an ATX supply.
In this figure, note the slight rise in PGOOD as the 5V supply
rises.The PGOOD output stage is made up of NMOS and
PMOS transistors. On the rising V
CC
, the PMOS device
becomes active slightly before the NMOS transistor pulls
“down”, generating the slight rise in the PGOOD voltage.
Note that Figure 5 shows the 12V gate driver voltage available
before the 5V supply to the HIP6311A has reached its
threshold level. If conditions were reversed and the 5V supply
was to rise first, the start-up sequence would be different. In
this case the HIP6311A will sense an over-current condition
due to charging the output capacitors. The supply will then
restart and go through the normal Soft-Start cycle.
Fault Protection
The HIP6311A protects the microprocessor and the entire
power system from damaging stress levels. Within the
HIP6311A both Over-Voltage and Over-Current circuits are
incorporated to protect the load and regulator.
Over-Voltage
The VSEN pin is connected to the microprocessor CORE
voltage. A CORE over-voltage condition is detected when
the VSEN pin goes more than 15% above the programmed
VID level.
The over-voltage condition is latched, disabling normal PWM
operation, and causing PGOOD to go low. The latch can
only be reset by lowering and returning V
CC
high to initiate a
POR and Soft-Start sequence.
During a latched over-voltage, the PWM outputs will be
driven either low or three state, depending upon the VSEN
input. PWM outputs are driven low when the VSEN pin
detects that the CORE voltage is 15% above the
programmed VID level. This condition drives the PWM
outputs low, resulting in the lower or synchronous rectifier
MOSFETS to conduct and shunt the CORE voltage to
ground to protect the load.
If after this event, the CORE voltage falls below the over-
voltage limit (plus some hysteresis), the PWM outputs will
three state. The HIP6601 family drivers pass the three state
information along, and shuts off both upper and lower
MOSFETs. This prevents “dumping” of the output capacitors
PWM 1
OUTPUT
PGOOD
V
CORE
5V
V
CC
V
IN
= 12V
DELAY TIME
FIGURE 3. START-UP OF 4 PHASE SYSTEM OPERATING AT
500kHz
PGOOD
V
CORE
5V
V
CC
V COMP
V
IN
= 12V
DELAY TIME
FIGURE 4. START-UP OF 4 PHASE SYSTEM OPERATING AT
200kHz
12V ATX
SUPPLY
PGOOD
5 V ATX
SUPPLY
V
CORE
ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”
V
IN
= 5V, CORE LOAD CURRENT = 31A
FREQUENCY 200kHz
FIGURE 5. SUPPLY POWERED BY ATX SUPPLY
HIP6311A
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HIP6311CB-T 功能描述:IC REG CTRLR BUCK PWM 20-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:4,000 系列:- PWM 型:電壓模式 輸出數:1 頻率 - 最大:1.5MHz 占空比:66.7% 電源電壓:4.75 V ~ 5.25 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 85°C 封裝/外殼:40-VFQFN 裸露焊盤 包裝:帶卷 (TR)
HIP6311CBZ 功能描述:電流型 PWM 控制器 2-4 PHS SYNCH BUCK CNTRLR 0 8%F RoHS:否 制造商:Texas Instruments 開關頻率:27 KHz 上升時間: 下降時間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數量:1 最大工作溫度:+ 105 C 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-14
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