
6
4325.1
November 3, 2005
The over-current function will trip at a peak inductor current
(I
PEAK
) determined by:
I
r
DS ON
(
)
where I
OCSET
is the internal OCSET current source (200
μ
A
- typical). The OC trip point varies mainly due to the
MOSFET’s r
DS(ON)
variations. To avoid over-current tripping
in the normal operating load range, find the R
OCSET
resistor
from the equation above with:
1. The maximum r
DS(ON)
at the highest junction temperature.
2. The minimum I
OCSET
from the specification table.
3. Determine
where
I is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
,
A small ceramic capacitor should be placed in parallel with
R
OCSET
to smooth the voltage across R
OCSET
in the
presence of switching noise on the input voltage.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible using ground
plane construction or single point grounding.
Figure 5 shows the critical power components of the
converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should be part
of ground or power plane in a printed circuit board. The
components shown in Figure 6 should be located as close
together as possible. Please note that the capacitors C
IN
and C
O
each represent numerous physical capacitors.
Locate the HIP6013 within 3 inches of the MOSFETs, Q1.
The circuit traces for the MOSFETs’ gate and source
connections from the HIP6013 must be sized to handle up to
1A peak current.
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C
ss
close to the SS pin because the internal current source is
only 10
μ
A. Provide local V
CC
decoupling between VCC and
GND pins. Locate the capacitor, C
BOOT
as close as practical
to the BOOT and PHASE pins.
O
S
0A
0V
TIME (20ms/DIV)
5A
10A
15A
2V
4V
FIGURE 4. OVER-CURRENT OPERATION
I
PEAK
---------------------------------------------------
=
I
PEAK
for I
PEAK
I
OUT MAX
)
I
(
)
2
+
>
FIGURE 5. PRINTED CIRCUIT BOARD
POWER AND GROUND PLANES OR ISLANDS
L
O
C
O
UGATE
PHASE
Q1
D2
V
IN
V
OUT
RETURN
HIP6013
C
IN
L
+12V
HIP6013
SS
GND
V
CC
BOOT
D1
L
O
C
O
V
OUT
L
Q1
D2
PHASE
FIGURE 6. PRINTED CIRCUIT BOARD
SMALL SIGNAL LAYOUT GUIDELINES
+V
IN
C
BOOT
C
VCC
C
SS
HIP6013