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參數(shù)資料
| 型號： | HIP6013CB |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO14 |
| 封裝： | SOIC-14 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 103K |
| 代理商： | HIP6013CB |
2-168
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(Vout) is regulated to the Reference voltage level. The error
amplifier (Error Amp) output (V
E/A
) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of Vin at the
PHASE node. The PWM wave is smoothed by the output
filter (Lo and Co).
The modulator transfer function is the small-signal transfer
function of Vout/V
E/A
. This function is dominated by a DC
Gain and the output filter (Lo and Co), with a double pole
break frequency at F
LC
and a zero at F
ESR
. The DC Gain of
the modulator is simply the input voltage (Vin) divided by the
peak-to-peak oscillator voltage
V
OSC
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the HIP6013) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180
o
.
The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
ST
Zero Below Filter’s Double Pole
(~75% F
LC
)
3. Place 2
ND
Zero at Filter’s Double Pole
4. Place 1
ST
Pole at the ESR Zero
5. Place 2
ND
Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high
gain peak do to the high Q factor of the output filter and is
not shown in Figure 8. Using the above guidelines should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F
P2
with the
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the log-log graph of Figure 8 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
o
.
Include worst case component variations when determining
phase margin.
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
OSC
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
-
+
REF
R1
R3
R2
C3
C2
C1
COMP
V
OUT
FB
Z
FB
HIP6013
Z
IN
COMPARATOR
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
Z
FB
F
LC =
L
O
2
π
C
O
--------------------------------------
F
ESR
=
O
)
--------------------------------------------
F
Z1
=
---------------------------------
F
P1
=
2
π
R2
---------------------
-----------------------------------------------------
F
Z2
=
----------------------------------------------------
F
P2
=
---------------------------------
HIP6013
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP6013CB-T | 功能描述:IC CONTROLLER PWM BUCK 14-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,000 系列:- 應(yīng)用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數(shù):10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應(yīng)商設(shè)備封裝:42-WLP 包裝:帶卷 (TR) |
| HIP6013CBZ | 功能描述:電壓模式 PWM 控制器 STD BUCK PWM/1 5%/14 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:1 拓?fù)浣Y(jié)構(gòu):Buck 輸出電壓:34 V 輸出電流: 開關(guān)頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel |
| HIP6013CBZ-T | 功能描述:電壓模式 PWM 控制器 STD BUCK PWM/1 5%/14 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:1 拓?fù)浣Y(jié)構(gòu):Buck 輸出電壓:34 V 輸出電流: 開關(guān)頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel |
| HIP6014 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor |
| HIP6014CB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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