- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385382 > HIP6013 (Intersil Corporation) FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN PDF資料下載
參數(shù)資料
| 型號： | HIP6013 |
| 廠商： | Intersil Corporation |
| 元件分類： | FPGA |
| 英文描述： | FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 降壓脈寬調(diào)制（PWM）控制器 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 103K |
| 代理商： | HIP6013 |
2-166
Functional Description
Initialization
The HIP6013 automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary.
The Power-On Reset (POR) function continually monitors
the input supply voltages and the enable (EN) pin. The POR
monitors the bias voltage at the VCC pin and the input
voltage (V
IN
) on the OCSET pin. The level on OCSET is
equal to V
IN
less a fixed voltage drop (see over-current
protection). With the EN pin held to VCC, the POR function
initiates soft start operation after both input supply voltages
exceed their POR thresholds. For operation with a single
+12V power source, V
IN
and V
CC
are equivalent and the
+12V power source must exceed the rising V
CC
threshold
before POR initiates operation.
The Power-On Reset (POR) function inhibits operation with
the chip disabled (EN pin low). With both input supplies
above their POR thresholds, transitioning the EN pin high
initiates a soft start interval.
Soft Start
The POR function initiates the soft start sequence. An
internal 10
μ
A current source charges an external capacitor
(C
SS
) on the SS pin to 4V. Soft start clamps the error
amplifier output (COMP pin) and reference input (+ terminal
of error amp) to the SS pin voltage. Figure 3 shows the soft
start interval with C
SS
= 0.1
μ
F. Initially the clamp on the
error amplifier (COMP pin) controls the converter’s output
voltage. At t1 in Figure 3, the SS voltage reaches the valley
of the oscillator’s triangle wave. The oscillator’s triangular
waveform is compared to the ramping error amplifier voltage.
This generates PHASE pulses of increasing width that
charge the output capacitor(s). This interval of increasing
pulse width continues to t2. With sufficient output voltage,
the clamp on the reference input controls the output voltage.
This is the interval between t2 and t3 in Figure 3. At t3 the
SS voltage exceeds the reference voltage and the output
voltage is in regulation. This method provides a rapid and
controlled output voltage rise.
Over-Current Protection
The over-current function protects the converter from a
shorted output by using the upper MOSFET’s on-resistance,
r
DS(ON)
to monitor the current. This method enhances the
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R
OCSET
)
programs the over-current trip level. An internal 200
μ
A
(typical) current sink develops a voltage across R
OCSET
that
is reference to V
IN
. When the voltage across the upper
MOSFET (also referenced to V
IN
) exceeds the voltage
across R
OCSET
, the over-current function initiates a soft-
start sequence. The soft-start function discharges C
SS
with
a 10
μ
A current sink and inhibits PWM operation. The soft-
start function recharges C
SS
, and PWM operation resumes
with the error amplifier clamped to the SS voltage. Should an
overload occur while recharging C
SS
, the soft start function
inhibits PWM operation while fully charging C
SS
to 4V to
complete its cycle. Figure 4 shows this operation with an
overload condition. Note that the inductor current increases
to over 15A during the C
SS
charging interval and causes an
over-current trip. The converter dissipates very little power
with this method. The measured input power for the
conditions of Figure 4 is 2.5W.
TIME (5ms/DIV)
SOFT-START
(1V/DIV)
0V
0V
t1
t2
t3
OUTPUT
VOLTAGE
(1V/DIV)
FIGURE 3. SOFT-START INTERVAL
HIP6013
相關PDF資料 |
PDF描述 |
|---|---|
| HIP6013CB | FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP6014 | Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor |
| HIP6014CB | Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor |
| HIP6016 | FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP6016CB | Advanced PWM and Dual Linear Power Control |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HIP6013_05 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Buck Pulse-Width Modulator (PWM) Controller |
| HIP6013CB | 功能描述:電流型 PWM 控制器 Buck PWM RoHS:否 制造商:Texas Instruments 開關頻率:27 KHz 上升時間: 下降時間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數(shù)量:1 最大工作溫度:+ 105 C 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-14 |
| HIP6013CB-T | 功能描述:IC CONTROLLER PWM BUCK 14-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,000 系列:- 應用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數(shù):10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應商設備封裝:42-WLP 包裝:帶卷 (TR) |
| HIP6013CBZ | 功能描述:電壓模式 PWM 控制器 STD BUCK PWM/1 5%/14 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:1 拓撲結構:Buck 輸出電壓:34 V 輸出電流: 開關頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel |
| HIP6013CBZ-T | 功能描述:電壓模式 PWM 控制器 STD BUCK PWM/1 5%/14 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:1 拓撲結構:Buck 輸出電壓:34 V 輸出電流: 開關頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。