
2-105
Figure 5 shows the critical power components of the
converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should be
part of ground or power plane in a printed circuit board. The
components shown in Figure 6 should be located as close
together as possible. Please note that the capacitors C
IN
and C
O
each represent numerous physical capacitors.
Locate the HIP6005A within 3 inches of the MOSFET, Q
1
.
The circuit traces for the MOSFET’s gate and source
connections from the HIP6005A must be sized to handle up
to 1A peak current.
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C
ss
close to the SS pin because the internal current source is
only 10
μ
A. Provide local V
CC
decoupling between V
CC
and
GND pins. Locate the capacitor, C
BOOT
as close as practical
to the BOOT and PHASE pins.
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a buck
converter. The output voltage (V
OUT
) is regulated to the
Reference voltage level. The error amplifier (Error Amp)
output (V
E/A
) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of V
IN
at the PHASE node. The
PWM wave is smoothed by the output filter (L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain and the output filter (L
O
and C
O
), with a double pole
break frequency at F
LC
and a zero at F
ESR
. The DC Gain of
the modulator is simply the input voltage (V
IN
) divided by the
peak-to-peak oscillator voltage
V
OSC
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the HIP6005A) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to
provide a closed loop transfer function with the highest 0dB
crossing frequency (f
0dB
) and adequate phase margin.
Phase margin is the difference between the closed loop
phase at f
0dB
and 180 degrees
.
The equations below relate
the compensation network’s poles, zeros and gain to the
components (R
1
, R
2
, R
3
, C
1
, C
2
, and C
3
) in Figure 8. Use
these guidelines for locating the poles and zeros of the
compensation network:
1. Pick Gain (R
2
/R
1
) for desired converter bandwidth
2. Place 1
ST
Zero Below Filter’s Double Pole (~75% F
LC
)
3. Place 2
ND
Zero at Filter’s Double Pole
4. Place 1
ST
Pole at the ESR Zero
5. Place 2
ND
Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
HIP6005A
SS
GND
V
CC
BOOT
D
1
L
O
C
O
V
OUT
L
Q
1
D
2
PHASE
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
+V
IN
C
BOOT
C
VCC
C
SS
+12V
V
OUT
OSC
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
FIGURE 7. VOLTAGE-MODE BUCK CONVERTER COMPEN-
SATION DESIGN
Z
IN
Z
FB
DACOUT
R
1
R
3
R
2
C
3
C
2
C
1
COMP
V
OUT
FB
Z
FB
HIP6005A
Z
IN
COMPARATOR
DETAILED COMPENSATION COMPONENTS
V
E/A
+
-
+
-
+
-
PHASE
F
LC
L
O
2
π
C
O
--------------------------------------
=
F
ESR
O
)
--------------------------------------------
=
HIP6005A