參數(shù)資料
型號: HIP6004BCB
廠商: INTERSIL CORP
元件分類: 穩(wěn)壓器
英文描述: Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor
中文描述: SWITCHING CONTROLLER, 215 kHz SWITCHING FREQ-MAX, PDSO20
封裝: PLASTIC, MS-013AC, SOIC-20
文件頁數(shù): 5/12頁
文件大?。?/td> 339K
代理商: HIP6004BCB
Functional Pin Descriptions
VSEN (Pin 1)
This pin is connected to the converters output voltage. The
PGOOD and OVP comparator circuits use this signal to
report output voltage status and for overvoltage protection.
OCSET (Pin 2)
Connect a resistor (R
OCSET
) from this pin to the drain of
the upper MOSFET. R
OCSET
, an internal 200
μ
A current
source (I
OCS
), and the upper MOSFET on-resistance
(r
DS(ON)
) set the converter over-current (OC) trip point
according to the following equation:
An over-current trip cycles the soft-start function.
SS (Pin 3)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10
μ
A current source, sets the soft-
start interval of the converter.
VID0-4 (Pins 4-8)
VID0-4 are the input pins to the 5-bit DAC. The states of
these five pins program the internal voltage reference
(DACOUT). The level of DACOUT sets the converter
output voltage. It also sets the PGOOD and OVP
thresholds. Table 1 specifies DACOUT for the all
combinations of DAC inputs.
COMP (Pin 9) and FB (Pin 10)
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.
GND (Pin 11)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
PGOOD (Pin 12)
PGOOD is an open collector output used to indicate the
status of the converter output voltage. This pin is pulled low
when the converter output is not within
±
10%
of the
DACOUT reference voltage. Exception to this behavior is
the ‘11111’ VID pin combination which disables the
converter; in this case PGOOD asserts a high level.
PHASE (Pin 13)
Connect the PHASE pin to the upper MOSFET source.
This pin is used to monitor the voltage drop across the
MOSFET for over-current protection. This pin also provides
the return path for the upper gate drive.
UGATE (Pin 14)
Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the upper MOSFET.
BOOT (Pin 15)
This pin provides bias voltage to the upper MOSFET driver.
A bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.
PGND (Pin 16)
This is the power ground connection. Tie the lower
MOSFET source to this pin.
LGATE (Pin 17)
Connect LGATE to the lower MOSFET gate. This pin
provides the gate drive for the lower MOSFET.
VCC (Pin 18)
Provide a 12V bias supply for the chip to this pin.
OVP (Pin 19)
The OVP pin can be used to drive an external SCR in the
event of an overvoltage condition. Output rising 15% more
than the DAC-set voltage triggers a high output on this pin
and disables PWM gate drive circuitry.
RT (Pin 20)
This pin provides oscillator switching frequency
adjustment. By placing a resistor (R
T
) from this pin to GND,
the nominal 200kHz switching frequency is increased
according to the following equation:
Conversely, connecting a pull-up resistor (R
T
) from this pin
to V
CC
reduces the switching frequency according to the
following equation:
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
VSEN
OCSET
SS
VID0
VID1
VID2
VID4
VID3
COMP
FB
RT
VCC
LGATE
PGND
OVP
BOOT
UGATE
PHASE
PGOOD
GND
I
PEAK
I
x R
DS ON
)
----------------------------------------------------
=
Fs
200kHz
6
T
)
--------------------
+
(R
T
to GND)
Fs
200kHz
7
T
)
--------------------
(R
T
to 12V)
HIP6004B
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