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參數(shù)資料
| 型號： | HIP6002CB |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Rectifier (PWM) Controller and Output Voltage Monitor |
| 中文描述： | SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO20 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 211K |
| 代理商： | HIP6002CB |
7
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
Figure 6 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of ground or power
plane in a printed circuit board. The components shown in
Figure 6 should be located as close together as possible.
Please note that the capacitors C
IN
and C
O
each represent
numerous physical capacitors. Locate the HIP6002 within 3
inches of the MOSFETs, Q1 and Q2. The circuit traces for the
MOSFETs’ gate and source connections from the HIP6002
must be sized to handle up to 1A peak current.
Figure 7 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C
SS
close to the SS pin because the internal current source is
only 10
μ
A. Provide local V
CC
decoupling between VCC and
GND pins. Locate the capacitor, C
BOOT
as close as practical
to the BOOT and PHASE pins.
Feedback Compensation
Figure 8 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the Reference voltage level. The error
amplifier (Error Amp) output (V
E/A
) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V
IN
at the
PHASE node. The PWM wave is smoothed by the output
filter (L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain and the output filter (L
O
and C
O
), with a double pole
break frequency at F
LC
and a zero at F
ESR
. The DC Gain of
the modulator is simply the input voltage (V
IN
) divided by the
peak-to-peak oscillator voltage
V
OSC
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the HIP6002) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to
provide a closed loop transfer function with the highest 0dB
crossing frequency (f
0dB
) and adequate phase margin.
Phase margin is the difference between the closed loop
phase at f
0dB
and 180 degrees
.
The equations below relate
the compensation network’s poles, zeros and gain to the
components (R1, R2, R3, C1, C2, and C3) in Figure 9. Use
these guidelines for locating the poles and zeros of the
compensation network:
BAND GAP
REFERENCE
1.26V
VID0
VID1
VID2
VID3
FB
COMP
DACOUT
ERROR
AMPLIFIER
21.5k
1.7k
10.7k
5.4k
2.7k
2.9k
DAC
FIGURE 5. DAC FUNCTION SCHEMATIC
+
-
+
-
PGND
L
O
C
O
LGATE
UGATE
PHASE
Q1
Q2
D2
V
IN
V
OUT
RETURN
HIP6002
C
IN
L
FIGURE 6. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
FIGURE 7. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
+12V
HIP6002
SS
GND
VCC
BOOT
D1
L
O
C
O
V
OUT
L
Q1
Q2
PHASE
+V
IN
C
BOOT
C
VCC
C
SS
F
LC
L
O
2
π
C
O
--------------------------------------
=
F
ESR
O
)
--------------------------------------------
=
HIP6002
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