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參數(shù)資料
| 型號： | HIP5062 |
| 廠商： | Intersil Corporation |
| 元件分類： | FPGA |
| 英文描述： | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 電源控制IC單芯片雙開關(guān)電源 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 655K |
| 代理商： | HIP5062 |
5
Pin Descriptions
PAD NUMBER
DESIGNATION
DESCRIPTION
1, 4, 7
S2
Source pads for the channel 2 regulator.
2, 3, 5, 6
D2
Drain pads for the channel 2 regulator.
8
V
DDP2
This pad is the power input for the channel 2 DMOS gate driver and also is used to decouple the
high current pulses to the output driver transistors. The decoupling capacitor should be at least
a 0.1
μ
F chip capacitor placed close to this pad and the DMOS source pads.
9
VCMP2
Output of the second channel transconductance amplifier. This node is used for both gain and
frequency compensation of the loop.
10
PSOK
This pad provides delayed positive indication when both supplies are enabled.
11
VREG2
Input to the transconductance error amplifier. The other common input for both amplifiers is
VINP, Pad 36.
12
FLTN
This is an open drain output that remains low when V+ is too low for proper operation. This node
and PSEN are useful in multiple converter configurations. This pad will be latched low when over-
temperature, over-voltage or over-current is experienced. V+ must be powered down to reset.
13
PSEN
This terminal is provided to activate the converter. When the input is low, the DMOS drivers are
disabled. There is an internal 12K pull-up resistor on this terminal.
14
SHRT
50
μ
A is internally applied to this node when there is an over-current condition.
15
SLRN
Control input to internal regulator that is used during the “start-up” of the supply. In normal oper-
ation this terminal starts at 0V and shuts down the internal regulator at approximately 9V. This
pad is usually connected to SFST, pad 16.
16
SFST
Controls the rate of rise of both output voltages. Time is determined by an internal 1
μ
A current
source and an external capacitor.
17
V
DDD
Voltage input for the chip’s digital circuits. This pad also allows decoupling of this supply.
18
V
DDA
This is the analog supply and internal 12V regulator output usually used only during the start-up
sequence. The internal regulator reduced to a nominal 9.2V when SLRN is returned to 12V. Out-
put current capability is 30mA at both voltages.
19
VREG1
Input to channel one transconductance error amplifier. The other, common input for both ampli-
fiers is VINP, pad 36.
20
V
DDP1
This pad is the power input for the channel 1 DMOS gate driver and also is used to decouple the
high current pulses to the output driver transistors. The decoupling capacitor should be at least
a 0.1
μ
F chip capacitor placed close to this pad and the DMOS source pads.
22, 23, 25, 26
D1
Drain pads for the channel 1 regulator.
21, 24, 27
S1
Source pads for the channel 1 regulator.
28
VTCN
Input to transconductance amplifier buffer for channel 1 only. Normally connected to VCMP1,
pad 29.
29
VCMP1
Output of the first channel transconductance amplifier. This node is used for both gain and fre-
quency compensation of the loop.
30
IRFO1
A resistor placed between this pad and IRFI1 converts the VCMP1 signal to a current for the cur-
rent sense comparator. The maximum current is set by the value of the resistor, according to the
equation: I
PEAK
= 16/R. Where R is the value of the external resistor in K
and must be greater
than 1.5K
but less than 10K
. For example, if the resistor chosen is 1.8K, the peak current will
be 8.8A. This assumes VCMP1 is 7.3V. Maximum output current should be kept below 10A.
31
IRFI1
See IRFO1.
HIP5062
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HIP5062DW | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP5062DY | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP5063 | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP5063DW | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| HIP5062DW | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Power Control IC Single Chip Dual Switching Power Supply |
| HIP5062DY | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Power Control IC Single Chip Dual Switching Power Supply |
| HIP5063 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Power Control IC Single Chip Power Supply |
| HIP5063DW | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Power Control IC Single Chip Power Supply |
| HIP5063DY | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Power Control IC Single Chip Power Supply |
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