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參數(shù)資料
| 型號： | HIP5060DY |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 20 A SWITCHING REGULATOR, 1100 kHz SWITCHING FREQ-MAX, UUC37 |
| 封裝： | DIE-37 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 615K |
| 代理商： | HIP5060DY |
5
Pin Descriptions
PAD NUMBER
DESIGNATION
DESCRIPTION
1
AGND
Analog ground.
2
VINP
Internal 5.1V reference.
3
SFST
Controls the rate of rise of the output voltage. Time is determined by an internal 0.7
μ
A current
source and an external capacitor.
4
IRFO
A resistor placed between this pad and IRFI converts the VCMP signal to a current for the current
sense comparator. The maximum current is set by the value of the resistor, according to the
equation: I
PEAK
= 32/R. Where R is the value of the external resistor in K
and must be greater
than 1.5K
but less than 10K
. For example, if the resistor chosen is 1.8K, the peak current will
be 17.8A. This assumes VCMP is 7.3V. Maximum output current should be kept below 20A.
5
IRFI
See IRFO
6
DGD2
Ground of the DMOS gate driver. This pad is used for bypassing.
7
V
DDD
Voltage input for the chip’s digital circuits. This pad also allows decoupling of this supply.
8
V
DDA
This is the analog supply and internal 12V regulator output.
9
V+
This is the main supply voltage input pad to the regulator IC. Because of the high peak currents
this pad must be well bypassed with at least a 0.7
μ
F capacitor and may be composed of seven,
single 0.1
μ
F chip capacitors.
10
SLCT
This pad provides for the option of using either internal 1MHz operation of for an external clock.
Floating or grounding this pad will place the internal clock at the CKIO pad. Returning this termi-
nal to V
DDD
or 12V will allow application of an external clock to the IC via the CKIO pad. There
is an internal 50K pull down
11
CKIO
Clock output when SLCT is floated or grounded. External clock input when SLCT is returned to
12V.
12
DGD1
This pad is the return for the digital supply.
13 & 14
V
DDP
These pads are used to decouple the high current pulses to the output driver transistors. The
capacitor should be at least a 0.1
μ
F chip capacitor placed close to this pad and the DMOS
source pads.
15, 16, 19, 20,
23, 24, 27, 28
S
Source pads of the DMOS power transistor.
17, 18, 21, 22,
25, 26, 29, 30
D
Drain pads of the DMOS power transistor.
31
TMON
This is the thermal shut down pad than can be used to disable the thermal shutdown circuit. By
returning this pad to 12V the function is disabled. Returning this pad to ground will put the IC into
the thermal shutdown state. Normally, this pad is left floating. Thermal shutdown occurs at a
nominal junction temperature of +125
o
C.
32
PSEN
This terminal is provided to activate the converter. This terminal may be left open or returned to
5V for normal operation. When the input is low, the DMOS driver is disabled.
33
SHRT
25
μ
A is internally applied to this node when there is an over-current condition.
34
PSOK
This pad provides a delayed positive indication when the supply is enabled.
35
VCMP
Output of the transconductance amplifier. This node is used for both gain and frequency com-
pensation of the loop.
36
VREG
Input to the transconductance error amplifier is available on this pad. The other input is internally
connected to the 5.1V reference, VINP, Pad 2.
37
FLTN
This is an open drain output that remains low when V+ is too low for proper operation. This node
and PSEN are useful in multiple converter configurations. This pad will be latched low when over-
temperature, over-voltage or over-current is experienced.
HIP5060
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