參數(shù)資料
型號: HIP4083AP
廠商: HARRIS SEMICONDUCTOR
元件分類: 功率晶體管
英文描述: 80V, 300mA Three Phase High Side Driver
中文描述: 3 CHANNEL, HALF BRDG BASED MOSFET DRIVER, PDIP16
文件頁數(shù): 4/10頁
文件大?。?/td> 70K
代理商: HIP4083AP
15
Pin Descriptions
PIN
NUMBER
SYMBOL
DESCRIPTION
6
11
16
AHB
BHB
CHB
(xHB)
Gate driver supplies. One external bootstrap diode and one capacitor are required for each. The bootstrap
diode and capacitor may be omitted when the HIP4083 is used to drive the lower gates in three phase full
bridge applications. In this case, tie all three xHB pins to V
DD
and tie the xHS pins to the sources of the
lower FETs. In full bridge applications, the lower FETs must be turned on first at start up to refresh the boot-
strap capacitors. In high side switch applications, the load will keep xHS low and refresh should happen
automatically at start up.
1
2
3
AHI
BHI
CHI
(xHI)
Logic level inputs. Logic at these three pins controls the three output drivers, AHO, BHO and CHO. When
xHI is low, xHO is high. When xHI is high, xHO is low. DIS (Disable) overrides all input signals. xHI can be
driven by signal levels of 0V to 15V (no greater than V
DD
). If these pins are not driven, an internal 100
μ
A
current source pulls them high.
5
V
SS
Chip ground.
13
UVLO
Undervoltage setting. A resistor can be connected between this pin and V
SS
to program the under voltage
set point - see Figure 7. With this pin not connected the undervoltage set point is typically 7V. When this
pin is tied to V
DD
, the undervoltage set point is typically 6.2V.
4
DIS
Disable input. Logic level input that when taken high sets all three outputs low. DIS high overrides all other
inputs. When DIS is taken low the outputs are controlled by the other inputs. DIS can be driven by signal
levels of 0V to 15V (no greater than V
DD
). An internal 100
μ
A pull-up holds DIS high when this pin is not
driven.
7
10
15
AHO
BHO
CHO
(xHO)
Gate connections. Connect to the gates of the power MOSFETs in each phase.
8
9
14
AHS
BHS
CHS
(xHS)
MOSFET source connection. Connect the sources of the power MOSFETs and the negative side of the
bootstrap capacitors to these pins. In high side switch applications, 2mA of current will flow out of these
pins into the load when the upper FETs are off. This current is necessary to guarantee that the upper FETs
stay off. This current tends to pull xHS high. For proper refresh, the load must pull the voltage on xHS down
to at least 7V below V
DD
. For example, when V
DD
= 12V, xHS must be pulled down to 5V. Therefore, the
minimum load necessary for proper refresh is given by the following equation: R
MIN
= 5V/2mA = 2.5k
. So
in this case, if the load has an impedance less than 5k
, refresh will happen automatically at start up.
12
V
DD
Positive supply rail. Bypass this pin to V
SS
with a capacitor
>
1
μ
F. In applications where the bus voltage and
chip V
DD
are at the same potential, it is a good idea to run a separate line from the supply to each. This
greatly simplifies the filtering requirements.
HIP4083
相關(guān)PDF資料
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