參數(shù)資料
型號(hào): HIP1016
廠商: Intersil Corporation
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Power Distribution Controllers(電源分配控制器)
中文描述: 配電控制器(電源分配控制器)
文件頁(yè)數(shù): 2/10頁(yè)
文件大?。?/td> 200K
代理商: HIP1016
2
Simplified Block Diagram
Pin Descriptions
+
-
I
SET
I
SEN
GATE
V
SS
V
DD
CTIM
PGOOD
PWRON
CLIM
WOCLIM
ENABLE
OC
10
μ
A
FALLING
EDGE
DELAY
18V
+
-
V
REF
+
-
1.86V
12V
+
-
R
R
S
QN
Q
ENABLE
POR
V
DD
8V
RISING
EDGE
PULSE
+
-
+
-
UV
18V
20
μ
A
7.5k
+
-
+
-
10
μ
A
PIN #
SYMBOL
FUNCTION
DESCRIPTION
1
ISET
Current Set
Connect to the low side of the current sense resistor through the current limiting set resistor.
This pin functions as the current limit programming pin.
2
ISEN
Current Sense
Connect to the more positive end of sense resistor to measure the voltage drop across this
resistor
3
GATE
External FET Gate Drive
Pin
Connecttothe gate ofthe external N-ChannelMOSFET. A capacitorfrom this nodetoground
sets the turn-on ramp. At turn-on this capacitor will be charged to V
DD
+5V (HIP1015) and to
V
DD
(HIP1016) by a 10
μ
A current source.
4
VSS
Chip Return
5
V
DD
Chip Supply
12V chip supply. This can be either connected directly to the +12V rail supplying the switched
load voltage or to a dedicated V
SS
+12V supply.
6
CTIM
Current Limit Timing
Capacitor
Connect a capacitor from this pin to ground. This capacitor determines the time delay
between an overcurrent event and chip output shutdown (current limit time-out). The duration
of current limit time-out (in seconds) = 93k
x C
TIM
(Farads).
7
PGOOD
Power Good Indicator
Indicates that the voltage on ISEN pin is within specification. PGOOD is driven by an open
drain N-Channel MOSFET and is pulled low when the output is not within specification.
8
PWRON
Power ON
PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is driven
high or is open. After a current limit time out, the chip is reset by a low level signal applied to
this pin. This input has 20
μ
A pull up capability
HIP1015, HIP1016
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