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參數(shù)資料
| 型號： | HI7191IPZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 21/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT PROGBL SER 20-PDIP |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 180 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 32.5mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極；1 個(gè)差分，雙極 |
5
FN4138.8
June 1, 2006
Input Logic Current, II
VIN = 0V, +5V
-
1.0
10
μA
Input Capacitance, CIN
VIN = 0V
-
5.0
-
pF
DIGITAL OUTPUTS
Output Logic High Voltage, VOH
IOUT = -100μA (Note 7)
2.4
-
V
Output Logic Low Voltage, VOL
IOUT = 3mA (Note 7)
-
0.4
V
Output Three-State Leakage Current,
IOZ
VOUT = 0V, +5V (Note 7)
-10
1
10
μA
Digital Output Capacitance, COUT
-10-
pF
TIMING CHARACTERISTICS
SCLK Minimum Cycle Time, tSCLK
200
-
ns
SCLK Minimum Pulse Width, tSCLKPW
50
-
ns
CS to SCLK Precharge Time, tPRE
50
-
ns
DRDY Minimum High Pulse Width
(Notes 2, 7)
500
-
ns
Data Setup to SCLK Rising Edge
(Write), tDSU
50
-
ns
Data Hold from SCLK Rising Edge
(Write), tDHLD
0-
-
ns
Data Read Access from Instruction Byte
Write, tACC
(Note 7)
-
40
ns
Read Bit Valid from SCLK Falling Edge,
tDV
(Note 7)
-
40
ns
Last Data Transfer to Data Ready
Inactive, tDRDY
(Note 7)
-
35
-
ns
RESET Low Pulse Width
(Note 2)
100
-
ns
SYNC Low Pulse Width
(Note 2)
100
-
ns
Oscillator Clock Frequency
(Note 2)
0.1
-
10
MHz
Output Rise/Fall Time
(Note 2)
-
30
ns
Input Rise/Fall Time
(Note 2)
-
1
μs
POWER SUPPLY CHARACTERISTICS
IAVDD
--
1.5
mA
IAVSS
--
2.0
mA
IDVDD
SCLK = 4MHz
-
3.0
mA
Power Dissipation, Active PDA
SB = ‘0’
-
15
32.5
mW
Power Dissipation, Standby PDS
SB = ‘1’
-
5
-
mW
PSRR
(Note 3)
-
70
-
dB
NOTES:
2. Parameter guaranteed by design or characterization, not production tested.
3. Applies to both bipolar and unipolar input ranges.
4. These errors can be removed by re-calibrating at the desired operating temperature.
5. Applies after system calibration.
6. Fully differential input signal source is used.
7. See Load Test Circuit, Figure 10, R1 = 10k
Ω, CL = 50pF.
8. 1 LSB = 298nV at 24 bits for a Full Scale Range of 5V.
9. VREF = VRHI - VRLO.
10. These errors are on the order of the output noise shown in Table 1.
11. All inputs except OSC1. The OSC1 input VIH is 3.5V minimum.
Electrical Specifications
AVDD = +5V, AVSS = -5V, DVDD = +5V, VRHI = +2.5V, VRLO = AGND = 0V, VCM = AGND,
PGIA Gain = 1, OSCIN = 10MHz, Bipolar Input Range Selected, fN = 10Hz (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HI7191
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