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參數(shù)資料
| 型號(hào)： | HI7191IB |
| 廠商： | Intersil |
| 文件頁數(shù)： | 10/25頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT PROGBL SER 20-SOIC |
| 標(biāo)準(zhǔn)包裝： | 38 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 32.5mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極；1 個(gè)差分，雙極 |
18
FN4138.8
June 1, 2006
Instruction Register
The Instruction Register is an 8-bit register which is used during
a communications cycle for setting up read/write operations.
R/W - Bit 7 of the Instruction Register determines whether a
read or write operation will be done following the instruction
byte load. 0 = READ, 1 = WRITE.
MB1, MB0 - Bits 6 and 5 of the Instruction Register
determine the number of bytes that will be accessed
following the instruction byte load. See Table 5 for the
number of bytes to transfer in the transfer cycle.
FSC
- Bit 4 is used to determine whether a Positive Full
Scale Calibration Register I/O transfer (FSC = 0) or a
Negative Full Scale Calibration Register I/O transfer
(FSC = 1) is being performed (see Table 6).
A3, A2, A1, A0 - Bits 3 and 2 (A3 and A2) of the Instruction
Register determine which internal register will be accessed
while bits 1 and 0 (A1 and A0) determine which byte of that
register will be accessed first. See Table 6 for the address
decode.
Write Operation
Data can be written to the Control Register, Offset
Calibration Register, Positive Full Scale Calibration Register,
and the Negative Full Scale Calibration Register. Write
operations are done using the SDIO, CS and SCLK lines
only, as all data is written into the HI7191 via the SDIO line
even when using the 3-wire configuration. Figures 14 and 15
show typical write timing diagrams.
The communication cycle is started by asserting the CS line
low and starting the clock from its idle state. To assert a write
cycle, during the instruction phase of the communication
cycle, the Instruction Byte should be set to a write transfer
(R/W = 1).
When writing to the serial port, data is latched into the
HI7191 on the rising edge of SCLK. Data can then be
changed on the falling edge of SCLK. Data can also be
changed on the rising edge of SCLK due to the 0ns hold time
required on the data. This is useful in pipelined applications
where the data is latched on the rising edge of the clock.
Read Operation - 3-Wire Transfer
Data can be read from the Data Output Register, Control
Register, Offset Calibration Register, Positive Full Scale
Calibration Register, and the Negative Full Scale Calibration
Register. When configured in 3-wire transfer mode, read
operations are done using the SDIO, SDO, CS and SCLK
lines. All data is read via the SDO line. Figures 16 and 17
show typical 3-wire read timing diagrams.
The communication cycle is started by asserting the CS line
and starting the clock from its idle state. To assert a read
cycle, during the instruction phase of the communication
cycle, the Instruction Byte should be set to a read transfer
(R/W = 0).
When reading the serial port, data is driven out of the HI7191
on the falling edge of SCLK. Data can be registered
externally on the next rising edge of SCLK.
Read Operation - 2-Wire Transfer
Data can be read from the Data Output Register, Control
Register, Offset Calibration Register, Positive Full Scale
Calibration Register, and the Negative Full Scale Calibration
Register. When configured in two-wire transfer mode, read
operations are done using the SDIO, CS and SCLK lines. All
data is read via the SDIO line. Figures 18 and 19 show
typical 2-wire read timing diagrams.
The communication cycle is started by asserting the CS line
and starting the clock from its idle state. To assert a read cycle,
during the instruction phase of the communication cycle, the
Instruction Byte should be set to a read transfer (R/W = 0).
When reading the serial port, data is driven out of the HI7191
on the falling edge of SCLK. Data can be registered
externally on the next rising edge of SCLK.
MSB
654321
LSB
R/W
MB1
MB0
FSC
A3
A2
A1
A0
TABLE 5. MULTIPLE BYTE ACCESS BITS
MB1
MB0
DESCRIPTION
0
Transfer 1 Byte
0
1
Transfer 2 Bytes
1
0
Transfer 3 Bytes
1
Transfer 4 Bytes
TABLE 6. INTERNAL DATA ACCESS DECODE STARTING BYTE
FSC A3A2A1A0
DESCRIPTION
X
0000
Data Output Register, Byte 0
X
0001
Data Output Register, Byte 1
X
0010
Data Output Register, Byte 2
X
0100
Control Register, Byte 0
X
0101
Control Register, Byte 1
X
0110
Control Register, Byte 2
X
1000
Offset Cal Register, Byte 0
X
1001
Offset Cal Register, Byte 1
X
1010
Offset Cal Register, Byte 2
0
1100
Positive Full Scale Cal Register, Byte 0
0
1101
Positive Full Scale Cal Register, Byte 1
0
1110
Positive Full Scale Cal Register, Byte 2
1
1100
Negative Full Scale Cal Register, Byte 0
1
1101
Negative Full Scale Cal Register, Byte 1
1
1110
Negative Full Scale Cal Register, Byte 2
HI7191
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