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參數(shù)資料
| 型號： | HI7190 |
| 廠商： | Intersil Corporation |
| 英文描述： | 24-Bit, High Precision, Sigma Delta A/D Converter(24位高精密∑-Δ A/D轉(zhuǎn)換器) |
| 中文描述： | 24位，精度高，Σ-ΔA / D轉(zhuǎn)換（24位高精密Σ-Δ的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 20/25頁 |
| 文件大?。?/td> | 472K |
| 代理商： | HI7190 |
20
FN3612.10
June 27, 2006
Control Register
The Control Register contains 24-bits to control the various
sections of the HI7190. This register is a read/write
register.
DC
- Bit 23 is the Data Coding Bit used to select between
two’s complementary and offset binary data coding. When
this bit is set (DC = 1) the data in the Data Output Register
will be two’s complement. When cleared (DC = 0) this data
will be offset binary. When operating in the unipolar mode
the output data is available in straight binary only (the DC bit
is ignored). This bit is cleared after a RESET is applied to the
part.
FP10 through FP0
- Bits 22 through 12 are the Filter
programming bits that determine the frequency response of
the digital filter. These bits determine the filter cutoff
frequency, the position of the first notch and the data rate of
the HI7190. The first notch of the filter is equal to the
decimation rate and can be determined by the formula:
f
NOTCH
= f
OSC
/(512 x CODE)
where CODE is the decimal equivalent of the value in FP10
through FP0. The values that can be programmed into these
bits are 10 to 2047 decimal, which allows a conversion rate
range of 9.54Hz to 1.953kHz when using a 10MHz clock.
IR WRITE PHASE
DATA TRANSFER PHASE - TWO-BYTE READ
CS
SCLK
SDIO
SDO
I0
I1
I2
I3
I4
I5
I6
I7
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11 B12
B13
B14
B15
FIGURE 17. DATA READ CYCLE, 3-WIRE CONFIGURATION, SCLK IDLE HIGH
THREE-STATE
THREE-STATE
IR WRITE PHASE
DATA TRANSFER PHASE - TWO-BYTE READ
CS
SCLK
SDIO
SDO
I0
I1
I2
I3
I4
I5
I6
I7
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
FIGURE 18. DATA READ CYCLE, 2-WIRE CONFIGURATION, SCLK IDLE LOW
THREE-STATE
THREE-STATE
IR WRITE PHASE
DATA TRANSFER PHASE - TWO-BYTE READ
CS
SCLK
SDIO
SDO
I0
I1
I2
I3
I4
I5
I6
I7
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11 B12
B13
B14
B15
FIGURE 19. DATA READ CYCLE, 2-WIRE CONFIGURATION, SCLK IDLE HIGH
BYTE 2
MSB
22
21
20
19
18
17
16
DC
FP10
FP9
FP8
FP7
FP6
FP5
FP4
BYTE 1
15
14
13
12
11
10
9
8
FP3
FP2
FP1
FP0
MD2
MD1
MD0
B/U
BYTE 0
7
6
5
4
3
2
1
LSB
G2
G1
G0
BO
SB
BD
MSB
SDL
HI7190
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參數(shù)描述 |
|---|---|
| HI7190 WAF | 制造商:Harris Corporation 功能描述: |
| HI7190_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:24-Bit, High Precision, Sigma Delta A/D Converter |
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