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參數(shù)資料
| 型號： | HI5813KIJ |
| 廠商： | INTERSIL CORP |
| 元件分類： | ADC |
| 英文描述： | CMOS 3.3V, 25 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP24 |
| 封裝： | CERDIP-24 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 153K |
| 代理商： | HI5813KIJ |
6-1809
Theory of Operation
HI5813 is a CMOS 12-Bit, Analog-to-Digital Converter that
uses
capacitor
charge
balancing
approximate the analog input. A binary weighted capacitor
network forms the A/D heart of the device. See the block
diagram for the HI5813.
to
successively
The capacitor network has a common node which is
connected to a comparator. The second terminal of each
capacitor is individually switchable to the input, V
REF
+ or
V
REF
-.
During the first three clock periods of a conversion cycle, the
switchable end of every capacitor is connected to the input
and the comparator is being auto balanced at the capacitor
common node.
During the fourth period, all capacitors are disconnected
from the input; the one representing the MSB (D11) is
connected to the V
REF
+ terminal; and the remaining
capacitors to V
REF
-. The capacitor common node, after the
charges balance out, will indicate whether the input was
above
1
/
2
of (V
REF
+ - V
REF
-). At the end of the fourth
period, the comparator output is stored and the MSB
capacitor is either left connected to V
REF
+ (if the comparator
was high) or returned to V
REF
-. This allows the next
comparison to be at either
3
/
4
or
1
/
4
of (V
REF
+ - V
REF
-).
At the end of periods 5 through 14, capacitors representing
D10 through D1 are tested, the result stored, and each
capacitor either left at V
REF
+ or at V
REF
-.
At the end of the 15th period, when the LSB (D0) capacitor is
tested, (D0) and all the previous results are shifted to the
output registers and drivers. The capacitors are reconnected
to the input, the comparator returns to the balance state, and
the data ready output goes active. The conversion cycle is
now complete.
Analog Input
The analog input pin is a predominately capacitive load that
changes between the track and hold periods of the
conversion cycle. During hold, clock period 4 through 15, the
input loading is leakage and stray capacitance, typically less
than 5
μ
A and 20pF.
At the start of input tracking, clock period 1, some charge is
dumped back to the input pin. The input source must have
low enough impedance to dissipate the current spike by the
end of the tracking period. The amount of charge is depen-
dent on supply and input voltages. The average current is
also proportional to clock frequency.
As long as these current spikes settle completely by end of
the signal acquisition period, converter accuracy will be
preserved. The analog input is tracked for 3 clock cycles.
With a clock of 500kHz the track period is 6
μ
s.
A simplified analog input model is presented in Figure 12.
During tracking, the A/D input (V
IN
) typically appears as a
380pF capacitor being charged through a 420
internal
switch resistance. The time constant is 160ns. To charge
this capacitor from an external “zero
” source to 0.5 LSB
(1/8192), the charging time must be at least 9 time
constants or 1.4
μ
s. The maximum source impedance
(R
SOURCE
Max) for a 6
μ
s acquisition time settling to within
0.5 LSB is 1.3k
.
If the clock frequency was slower, or the converter was not
restarted immediately (causing a longer sample time), a
higher source impedance could be tolerated.
Reference Input
The reference input V
REF
+ should be driven from a low
impedance source and be well decoupled.
Current spikes are generated on the reference pin during
each bit test of the successive approximation part of the con-
version cycle as the charge balancing capacitors are
switched between V
REF
- and V
REF
+ (clock periods 5 - 14).
These current spikes must settle completely during each bit
test of the conversion to not degrade the accuracy of the
converter. Therefore V
REF
+ and V
REF
- should be well
bypassed. Reference input V
REF
- is normally connected
directly to the analog ground plane. If V
REF
- is biased for
nulling the converters offset it must be stable during the
conversion cycle.
Full Scale and Offset Adjustment
In many applications the accuracy of the HI5813 would be
sufficient without any adjustments. In applications where
accuracy is of utmost importance full scale and offset errors
may be adjusted to zero.
The V
REF
+ and V
REF
- pins reference the two ends of the
analog input range and may be used for offset and full scale
adjustments. In a typical system the V
REF
- might be
returned to a clean ground, and the offset adjustment done
on an input amplifier. V
REF
+ would then be adjusted to null
out the full scale error. When this is not possible, the V
REF
-
input can be adjusted to null the offset error, however, V
REF
-
must be well decoupled.
Full scale and offset error can also be adjusted to zero in the
signal conditioning amplifier driving the analog input (V
IN
).
Control Signal
The HI5813 may be synchronized from an external source
by using the STRT (Start Conversion) input to initiate conver-
sion, or if STRT is tied low, may be allowed to free run. Each
conversion cycle takes 15 clock periods.
The input is tracked from clock period 1 through period 3,
then disconnected as the successive approximation takes
place. After the start of the next period 1 (specified by t
D
data), the output is updated.
R
SOURCE
V
IN
R
SW
≈
420
C
SAMPLE
≈
380pF
R
SOURCE (MAX)
=
-t
ACQ
C
SAMPLE
ln [2
-(N + 1)
]
- R
SW
FIGURE 12. ANALOG INPUT MODEL IN TRACK MODE
HI5813
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI5813KIP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HI5816KIA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 12-Bit |
| HI5816KIB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HI5816KIP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HI5828 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, 125+MSPS, CommLink⑩ Dual High Speed CMOS D/A (2.7V-5.5V) |
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