參數(shù)資料
型號: HI5813
廠商: Intersil Corporation
英文描述: CMOS 25Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold(CMOS 12位片內帶跟蹤和保持電路的ADC)
中文描述: 的CMOS 25Microsecond,12位,采樣的A / D轉換器內部跟蹤和保持的CMOS(12位片內帶跟蹤和保持電路的ADC)的
文件頁數(shù): 4/11頁
文件大小: 153K
代理商: HI5813
6-1805
Input Bandwidth -3dB
-
1
-
-
MHz
Reference Input Current
-
160
-
-
-
μ
A
Input Series Resistance, R
S
In Series with Input
C
SAMPLE
-
420
-
-
-
Input Capacitance, C
SAMPLE
During Sample State
-
380
-
-
-
pF
Input Capacitance, C
HOLD
During Hold State
-
20
-
-
-
pF
DIGITAL INPUTS
OEL, OEM, STRT
High-Level Input Voltage, V
IH
2.4
-
-
2.4
-
V
Low-Level Input Voltage, V
IL
-
-
0.8
-
0.8
V
Input Leakage Current, I
IL
Except CLK, V
IN
= 0V, 5V
-
-
±
10
-
±
10
μ
A
Input Capacitance, C
IN
-
10
-
-
pF
DIGITAL OUTPUTS
High-Level Output Voltage, V
OH
I
SOURCE
= -400
μ
A
2.6
-
-
2.6
-
V
Low-Level Output Voltage, V
OL
I
SINK
= 1.6mA
-
-
0.4
-
0.4
V
Three-State Leakage, I
OZ
Except DRDY, V
OUT
= 0V,
3.3V
-
-
±
10
-
±
10
μ
A
Output Capacitance, C
OUT
Except DRDY
-
20
-
-
-
pF
TIMING
Conversion Time (t
CONV
+ t
ACQ
)
(Includes Acquisition Time)
J
25
-
-
25
-
μ
s
K
30
-
-
30
-
μ
s
Clock Frequency
(Note 2)
0.05
-
0.75
0.05
0.75
MHz
Clock Pulse Width, t
LOW
, t
HIGH
(Note 2)
100
-
-
100
-
ns
Aperture Delay, t
D
APR
(Note 2)
-
35
50
-
70
ns
Clock to Data Ready Delay, t
D1
DRDY
(Note 2)
-
180
210
-
240
ns
Clock to Data Ready Delay, t
D2
DRDY
(Note 2)
-
180
220
-
250
ns
Start Removal Time, t
R
STRT
(Note 2)
75
30
-
75
-
ns
Start Setup Time, t
SU
STRT
(Note 2)
85
60
-
30
-
ns
Start Pulse Width, t
W
STRT
(Note 2)
-
15
25
-
25
ns
Start to Data Ready Delay, t
D3
DRDY
(Note 2)
-
110
130
-
160
ns
Output Enable Delay, t
EN
(Note 2)
-
65
75
-
80
ns
Output Disabled Delay, t
DIS
(Note 2)
-
95
110
-
130
ns
POWER SUPPLY CHARACTERISTICS
Supply Current, I
DD
+ I
AA
-
0.5
1
-
2.5
mA
NOTE:
2. Parameter guaranteed by design or characterization, not production tested.
Electrical Specifications
V
DD
= V
AA
+ = V
REF
+ = 3.3V, V
SS
= V
AA
- = V
REF
- = GND, CLK = 600kHz (J suffix),
CLK = 500kHz (K suffix), Unless Otherwise Specified
(Continued)
PARAMETER
TEST CONDITIONS
25
o
C
-
40
o
C TO 85
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
HI5813
相關PDF資料
PDF描述
HI5813JIB CMOS 3.3V, 25 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold
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相關代理商/技術參數(shù)
參數(shù)描述
HI5813_01 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 3.3V, 25 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold
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