參數(shù)資料
型號: HI5812JIP
廠商: Intersil
文件頁數(shù): 5/16頁
文件大小: 0K
描述: ADC 12BIT 50KSPS 1.5LSB 24-DIP
標(biāo)準(zhǔn)包裝: 15
位數(shù): 12
采樣率(每秒): 50k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 25mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 24-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 24-PDIP
包裝: 管件
輸入數(shù)目和類型: 1 個(gè)單端,單極
13
Effective Number of Bits
The effective number of bits (ENOB) is derived from the
SINAD data;
Total Harmonic Distortion
The total harmonic distortion (THD) is the ratio of the RMS
sum of the second through sixth harmonic components to
the fundamental RMS signal for a specified input and
sampling frequency.
Spurious-Free Dynamic Range
The spurious-free dynamic range (SFDR) is the ratio of the
fundamental RMS amplitude to the RMS amplitude of the
next largest spur or spectral component. If the harmonics
are buried in the noise floor it is the largest peak.
ENOB =
SINAD - 1.76
6.02
THD = 10 Log
Total Harmonic Power (2nd - 6th Harmonic)
Sinewave Signal Power
SFDR = 10 Log
Sinewave Signal Power
Highest Spurious Signal Power
TABLE 2. CODE TABLE
CODE
DESCRIPTION
INPUT VOLTAGE
VREF+ = 4.608V
VREF- = 0.0V
(V)
DECIMAL
COUNT
BINARY OUTPUT CODE
MSB
LSB
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Full Scale (FS)
4.6069
4095
1
FS - 1 LSB
4.6058
4094
1
0
3/
4 FS
3.4560
3072
1
0
1/
2 FS
2.3040
2048
1
0
1/
4 FS
1.1520
1024
0
1
0
1 LSB
0.001125
1
0
1
Zero
0
The voltages listed above represent the ideal lower transition of each output code shown as a function of the reference voltage.
0.01
F
0.1
F
10
F
4.7
F
VREF+
VIN
VAA+VDD
D11
D0
DRDY
OEM
OEL
STRT
CLK
0.1
F
VREF-
VAA-
VSS
+5V
OUTPUT
DATA
750kHz CLOCK
0.001
F
0.1
F
4.7
F
VREF
ANALOG
INPUT
.
FIGURE 22. GROUND AND SUPPLY DECOUPLING
HI5812
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