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參數(shù)資料
| 型號： | HI5762 |
| 廠商： | Intersil Corporation |
| 英文描述： | Dual 10-Bit, 60MSPS A/D Converter(雙路、10位采樣速率為60MSPS的A/D轉(zhuǎn)換器) |
| 中文描述： | 雙10位，60MSPS的A / D轉(zhuǎn)換器（雙路，10位采樣速率為60MSPS的的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 107K |
| 代理商： | HI5762 |
3-10
Detailed Description
Theory of Operation
The HI5762 is a dual 10-bit fully differential sampling pipeline
A/D converter with digital error correction logic. Figure 15
depicts the circuit for the front end differential-in-differential-
out sample-and-hold (S/H) amplifiers. The switches are
controlled by an internal sampling clock which is a non-
overlapping two phase signal
, Φ
1
and
Φ
2
, derived from the
master sampling clock. During the sampling phase,
Φ
1
, the
input signal is applied to the sampling capacitors, C
S
. At the
same time the holding capacitors, C
H
, are discharged to
analog ground. At the falling edge of
Φ
1
the input signal is
sampled on the bottom plates of the sampling capacitors. In
the next clock phase,
Φ
2
, the two bottom plates of the
sampling capacitors are connected together and the holding
capacitors are switched to the op amp output nodes. The
charge then redistributes between C
S
and C
H
completing one
sample-and-hold cycle. The front end sample-and-hold output
is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-and-
hold function but will also convert a single-ended input to a
fully-differential output for the converter core. During the
sampling phase, the I/Q
IN
pins see only the on-resistance of a
switch and C
S
. The relatively small values of these
components result in a typical full power input bandwidth of
250MHz for the converter.
FIGURE 13. SUPPLY CURRENT vs TEMPERATURE
FIGURE 14. 2048 POINT FFT PLOT
Typical Performance Curves
(Continued)
S
0
-40
140
120
100
80
60
40
20
TEMPERATURE (
o
C)
0
20
40
60
80
-20
f
S
= 60MSPS
1MHz < f
IN
< 15MHz
AI
CC
I
CC
DI
CC1
DI
CC2
DI
CC3
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-1000
100
200
300
400
500
600
700
800
900
1023
FREQUENCY (BIN)
d
f
S
= 60MSPS
f
IN
= 10MHz
T
A
= 25
o
C
TABLE 1. A/D CODE TABLE
CODE CENTER
DESCRIPTION
DIFFERENTIAL INPUT
VOLTAGE
(I/Q
IN
+ - I/Q
IN
-)
OFFSET BINARY OUTPUT CODE
MSB
LSB
I/QD9 I/QD8 I/QD7 I/QD6 I/QD5 I/QD4 I/QD3 I/QD2 I/QD1 I/QD0
+Full Scale (+FS) -
1
/
4
LSB
+FS
-
1
1
/
4
LSB
+
3
/
4
LSB
-
1
/
4
LSB
-FS + 1
3
/
4
LSB
-Full Scale (-FS) +
3
/
4
LSB
0.499756V
1
1
1
1
1
1
1
1
1
1
0.498779V
1
1
1
1
1
1
1
1
1
0
732.422
μ
V
1
0
0
0
0
0
0
0
0
0
-244.141
μ
V
0
1
1
1
1
1
1
1
1
1
-0.498291V
0
0
0
0
0
0
0
0
0
1
-0.499268V
0
0
0
0
0
0
0
0
0
0
NOTE:
8. The voltages listed above represent the ideal center of each output code shown with V
REFIN
= +2.5V.
-
+
+
-
C
H
C
S
C
S
C
H
I/Q
IN+
V
OUT+
V
OUT-
I/Q
IN-
Φ
1
Φ
1
Φ
1
Φ
2
Φ
1
Φ
1
Φ
1
FIGURE 15. ANALOG INPUT SAMPLE-AND-HOLD
HI5762
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI5762/4IN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
| HI5762/6IN | 功能描述:CONV A/DDUAL 10BIT 60MSPS 44MQFP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| HI5762/6INZ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC W/ANNEAL 44L MQFP IN A/D 10B 60MSPS VREF RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| HI5762_10 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual 10-Bit, 60MSPS A/D Converter with Internal Voltage Reference |
| HI5762EVAL2 | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 EVAL MODULA DVIC TYPE HI5762 AMP RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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