
8
FN4318.3
January 22, 2010
Digital Supply Voltage, DVCC1 and DVCC2
4.75
5.0
5.25
V
Digital Output Supply Voltage, DVCC3
2.7
3.0
3.3
V
4.75
5.0
5.25
V
Supply Current, ICC
fS = 60MSPS
-
130
-
mA
Power Dissipation
-
650
670
mW
Offset Error Sensitivity,
ΔV
OS
AVCC or DVCC = 5V ±5%
-
±0.5
-
LSB
Gain Error Sensitivity,
ΔFSE
AVCC or DVCC = 5V ±5%
-
±0.6
-
LSB
NOTES:
4. Limits established by characterization and are not production tested.
5. With the clock low and DC input.
Electrical Specifications
AVCC1,2 = DVCC1,2 = +5.0V, DVCC3 = +3.0V; VRIN = 2.50V; fS = 60MSPS at 50% Duty Cycle;
CL = 10pF; TA = +25°C; Differential Analog Input; Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Timing Waveforms
NOTES:
6. SN: N-th sampling period.
7. HN: N-th holding period.
8. BM, N: M-th stage digital output corresponding to N-th sampled input.
9. DN: Final data output corresponding to N-th sampled input.
FIGURE 1. HI5762 INTERNAL CIRCUIT TIMING
DN - 6
DN - 5
DN - 1
DN
DN + 1
DN + 2
ANALOG
INPUT
CLOCK
INPUT
S/H
1ST
STAGE
2ND
STAGE
9TH
STAGE
DATA
OUTPUT
SN - 1 HN - 1
SN
HN
SN + 1 HN + 1 SN + 2
SN + 5 HN + 5 SN + 6 HN + 6 SN + 7 HN + 7 SN + 8 HN + 8
B1, N - 1
B1, N
B1, N + 1
B1, N + 4
B1, N + 5
B1, N + 6
B1, N + 7
B2, N - 2
B2, N - 1
B2, N
B2, N + 4
B2, N + 5
B2, N + 6
B9, N - 5
B9, N - 4
B9, N
B9, N + 1
B9, N + 2
B9, N + 3
tLAT
HI5762