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參數(shù)資料
| 型號： | HI5746KCBZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 0K |
| 描述： | CONV A/D 10BIT 40MSPS 28-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 40M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 功率耗散（最大）： | 275 mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 剪切帶 (CT) |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，雙極 |
| 其它名稱： | HI5746KCBZ-TCT |
14
The output enable pin, OE, when pulled high will three-state
the digital outputs to a high impedance state. Set the OE
input to logic low for normal operation.
Supply and Ground Considerations
The HI5746 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
path. The digital data outputs also have a separate supply
pin, DVCC2 , which can be powered from a 3V or 5V supply.
This allows the outputs to interface with 3V logic if so
desired.
The part should be mounted on a board that provides
separate low impedance connections for the analog and
digital supplies and grounds. For best performance, the
supplies to the HI5746 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as
possible to the converter. If the part is powered off a single
supply then the analog supply should be isolated with a
ferrite bead from the digital supply.
Refer to the application note “Using Intersil High Speed A/D
Converters” (AN9214) for additional considerations when
using high speed converters.
Static Performance Definitions
Offset Error (VOS)
The midscale code transition should occur at a level 1/4 LSB
above half-scale. Offset is defined as the deviation of the
actual code transition from this point.
Full-Scale Error (FSE)
The last code transition should occur for an analog input that
is 3/4 LSB below positive Full scale (+FS) with the offset
error removed. Fullscale error is defined as the deviation of
the actual code transition from this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
Power Supply Sensitivity
Each of the power supplies are moved plus and minus 5%
and the shift in the offset and full scale error (in LSBs) is
noted.
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to evaluate
the dynamic performance of the HI5746. A low distortion sine
wave is applied to the input, it is coherently sampled, and the
output is stored in RAM. The data is then transformed into the
frequency domain with an FFT and analyzed to evaluate the
dynamic performance of the A/D. The sine wave input to the
part is -0.5dB down from Fullscale for all these tests.
TABLE 1. A/D CODE TABLE
CODE CENTER
DESCRIPTION
DIFFERENTIAL
INPUT VOLTAGE
(VIN+ - VIN-)
OFFSET BINARY OUTPUT CODE
(DFS LOW)
TWO’S COMPLEMENT OUTPUT CODE
(DFS HIGH)
M
S
B
L
S
B
M
S
B
L
S
B
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
+Full Scale (+FS) -
1/
4 LSB
0.499756V
1
0
1
+FS
- 11/4 LSB
0.498779V
1
0
1
0
+3/4 LSB
732.422
V
1
0
-1/4 LSB
-244.141
V
0
1
-FS + 13/4 LSB
-0.498291V
0
1
0
1
-Full Scale (-FS) +
3/
4 LSB
-0.499268V
0
1
0
NOTES:
8. The voltages listed above represent the ideal center of each output code shown as a function of the reference differential voltage,
(VREF + - VREF-) = 0.5V.
9. VREF+ = 2.5V and VREF- = 2V.
OE INPUT
DIGITAL DATA OUTPUTS
0
Active
1
High Impedance
HI5746
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