1DVEE3 GND (With a Single Power Supply) Digital Power Supply. Ground for ECL input. -5V for PECL and T" />
參數(shù)資料
型號(hào): HI3026JCQ
廠商: Intersil
文件頁(yè)數(shù): 15/17頁(yè)
文件大?。?/td> 0K
描述: ADC FLASH 8BIT 120MSPS 48-PQFP
標(biāo)準(zhǔn)包裝: 60
位數(shù): 8
采樣率(每秒): 120M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
工作溫度: -20°C ~ 75°C
安裝類型: 表面貼裝
封裝/外殼: 44-BQFP
供應(yīng)商設(shè)備封裝: 48-MQFP(12x12)
包裝: 托盤
輸入數(shù)目和類型: 1 個(gè)單端,單極
7
1DVEE3
GND (With a Single
Power Supply)
Digital Power Supply. Ground for ECL
input. -5V for PECL and TTL input.
+5V (Typ) (With Dual
Power Supplies)
16, 17,
18
NC
No Connect pin. Not connected with
the internal circuits.
13
CLK/E
I
ECL/PECL
Clock Input.
14
CLK/NE
I
CLK/E Complementary Input. When left
open, this pin goes to the threshold
potential. Only CLK/E can be used for
operation, but complementary input is
recommended to attain fast and stable
operation.
48
RESETN/E
I
Reset Input. When the input is set to low
level, the built-in CLK frequency divider
circuit can be reset.
47
RESET/E
I
RESETN/E Complementary Input.
When left open, this pin goes to the
threshold voltage. Only RESETN/E
can be used for operation.
15
CLK/T
I
TTL
Clock input.
46
RESETN/T
I
Reset Input. When left open, this input
goes to high level. When the input is
set to low level, the built-in CLK
frequency divider circuit can be reset.
44
INV
I
TTL
Data Output Polarity Inversion Input.
When left open, this input goes to high
level. (See Table 1; I/O Correspondence
Table).
45
SELECT
VCC or Ground
Data Output Mode Selection. (See
Table 2; Operating Mode Table).
Pin Descriptions (Continued)
PIN NO
SYMBOL
I/O
TYPICAL
VOLTAGE LEVEL
EQUIVALENT CIRCUIT
DESCRIPTION
13 48
47
14
DGND3
DVEE3
1.2V
R
RR
46
15
DVCC1
1.5V
R
R/2
DGND1
DVEE3
44
DVCC1
DGND1
DVEE3
45
DVCC1
DGND1
DVEE3
HI3026
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